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authorUwe Hermann <uwe@hermann-uwe.de>2010-09-27 17:53:17 +0000
committerUwe Hermann <uwe@hermann-uwe.de>2010-09-27 17:53:17 +0000
commit5211a7023e90580505acc4eda855206540f588c7 (patch)
treed45dc1028f52a8778ef5b5c417c27a1ec9402360 /src/cpu/x86/fpu_enable.inc
parentda28cd85428f8469d8de8c083b7fe950941bbc08 (diff)
downloadcoreboot-5211a7023e90580505acc4eda855206540f588c7.tar.xz
Add a few missing license headers based on svn logs, and also add a
few more code comments to src/cpu/x86/*.inc files. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5859 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/x86/fpu_enable.inc')
-rw-r--r--src/cpu/x86/fpu_enable.inc39
1 files changed, 34 insertions, 5 deletions
diff --git a/src/cpu/x86/fpu_enable.inc b/src/cpu/x86/fpu_enable.inc
index bd7a7ff630..f3eedcdaf6 100644
--- a/src/cpu/x86/fpu_enable.inc
+++ b/src/cpu/x86/fpu_enable.inc
@@ -1,10 +1,39 @@
- /* preserve BIST in %eax */
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2002 Eric Biederman <ebiederm@xmission.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
__fpu_start:
- movl %eax, %ebp
+ /* Preserve BIST. */
+ movl %eax, %ebp
- /* Disable floating point emulation */
+ /*
+ * Clear the CR0[2] bit (the "Emulation" flag, EM).
+ *
+ * This indicates that the processor has an (internal or external)
+ * x87 FPU, i.e. floating point operations will be executed by the
+ * hardware (and not emulated in software).
+ *
+ * Additionally, if this bit is not cleared, MMX/SSE instructions won't
+ * work, i.e., they will trigger an invalid opcode exception (#UD).
+ */
movl %cr0, %eax
- andl $~(1<<2), %eax
+ andl $~(1 << 2), %eax
movl %eax, %cr0
- movl %ebp, %eax
+ /* Restore BIST. */
+ movl %ebp, %eax