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authorRonald G. Minnich <rminnich@chromium.org>2012-06-05 14:41:27 -0700
committerStefan Reinauer <stefan.reinauer@coreboot.org>2012-11-13 16:07:45 +0100
commit8b93059eccedc528443c06eb86c58bd320dca203 (patch)
tree65b3dd93170d53a6ba8dfb9ce63a347e95339f5b /src/cpu/x86/lapic/secondary.S
parent455f4b432835828e82531adf967b9c7d8fc812dc (diff)
downloadcoreboot-8b93059eccedc528443c06eb86c58bd320dca203.tar.xz
Pass the CPU index as a parameter to startup.
This addition is in support of future multicore support in coreboot. It also will allow us to remove some asssembly code. The CPU "index" -- i.e., its order in the sequence in which cores are brought up, NOT its APIC id -- is passed into the secondary start. We modify the function to specify regparm(0). We also take this opportunity to do some cleanup: indexes become unsigned ints, not unsigned longs, for example. Build and boot on a multicore system, with pcserial enabled. Capture the output. Observe that the messages Initializing CPU #0 Initializing CPU #1 Initializing CPU #2 Initializing CPU #3 appear exactly as they do prior to this change. Change-Id: I5854d8d957c414f75fdd63fb017d2249330f955d Signed-off-by: Ronald G. Minnich <rminnich@chromium.org> Reviewed-on: http://review.coreboot.org/1820 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/cpu/x86/lapic/secondary.S')
-rw-r--r--src/cpu/x86/lapic/secondary.S2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/cpu/x86/lapic/secondary.S b/src/cpu/x86/lapic/secondary.S
index ec1bd9c4d4..045454e2ed 100644
--- a/src/cpu/x86/lapic/secondary.S
+++ b/src/cpu/x86/lapic/secondary.S
@@ -53,6 +53,8 @@ __ap_protected_start:
/* Set the stack pointer, and flag that we are done */
xorl %eax, %eax
movl secondary_stack, %esp
+ movl secondary_cpu_index, %edi
+ pushl %edi
movl %eax, secondary_stack
call secondary_cpu_init