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authorStefan Reinauer <reinauer@chromium.org>2011-11-02 16:12:34 -0700
committerStefan Reinauer <stefan.reinauer@coreboot.org>2012-03-30 01:07:49 +0200
commit00093a81d3f54c72215d9f402c3f88880da89a81 (patch)
tree9e36867db1a94d195fdf69be11c3e847800ab82c /src/cpu/x86/lapic
parent1afe51af83ad0beb3f0ace1085524b327ecff7c6 (diff)
downloadcoreboot-00093a81d3f54c72215d9f402c3f88880da89a81.tar.xz
Add an option to keep the ROM cached after romstage
Change-Id: I05f1cbd33f0cb7d80ec90c636d1607774b4a74ef Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/739 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/cpu/x86/lapic')
-rw-r--r--src/cpu/x86/lapic/Makefile.inc1
-rw-r--r--src/cpu/x86/lapic/boot_cpu.c3
2 files changed, 3 insertions, 1 deletions
diff --git a/src/cpu/x86/lapic/Makefile.inc b/src/cpu/x86/lapic/Makefile.inc
index af20956a9a..f3fcadc0a7 100644
--- a/src/cpu/x86/lapic/Makefile.inc
+++ b/src/cpu/x86/lapic/Makefile.inc
@@ -2,3 +2,4 @@ ramstage-y += lapic.c
ramstage-y += lapic_cpu_init.c
ramstage-y += secondary.S
ramstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c
+ramstage-y += boot_cpu.c
diff --git a/src/cpu/x86/lapic/boot_cpu.c b/src/cpu/x86/lapic/boot_cpu.c
index 87418d0883..0fb9d5d35c 100644
--- a/src/cpu/x86/lapic/boot_cpu.c
+++ b/src/cpu/x86/lapic/boot_cpu.c
@@ -1,7 +1,8 @@
+#include <cpu/x86/lapic.h>
#include <cpu/x86/msr.h>
#if CONFIG_SMP
-static int boot_cpu(void)
+int boot_cpu(void)
{
int bsp;
msr_t msr;