diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2016-08-21 10:12:15 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-08-23 15:43:58 +0200 |
| commit | d6e96864c9245b82222dada6fea2b89ccb7fecfd (patch) | |
| tree | 9d850d9cfc15d19792da114d426009cc6fb208fa /src/cpu/x86/lapic | |
| parent | 38424987c6d19015e4572d5371a0f9f621fc46fa (diff) | |
| download | coreboot-d6e96864c9245b82222dada6fea2b89ccb7fecfd.tar.xz | |
src/cpu: Capitalize CPU, APIC and IOAPIC typo fix
Change-Id: I82e0736dc6b44cfcc57cdfdc786c85c4b6882260
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16276
Tested-by: build bot (Jenkins)
Reviewed-by: Omar Pakker
Diffstat (limited to 'src/cpu/x86/lapic')
| -rw-r--r-- | src/cpu/x86/lapic/apic_timer.c | 2 | ||||
| -rw-r--r-- | src/cpu/x86/lapic/lapic.c | 8 | ||||
| -rw-r--r-- | src/cpu/x86/lapic/lapic_cpu_init.c | 4 |
3 files changed, 7 insertions, 7 deletions
diff --git a/src/cpu/x86/lapic/apic_timer.c b/src/cpu/x86/lapic/apic_timer.c index b16521a56d..41edde913f 100644 --- a/src/cpu/x86/lapic/apic_timer.c +++ b/src/cpu/x86/lapic/apic_timer.c @@ -83,7 +83,7 @@ static inline u32 get_timer_fsb(void) void init_timer(void) { - /* Set the apic timer to no interrupts and periodic mode */ + /* Set the APIC timer to no interrupts and periodic mode */ lapic_write(LAPIC_LVTT, (LAPIC_LVT_TIMER_PERIODIC | LAPIC_LVT_MASKED)); /* Set the divider to 1, no divider */ diff --git a/src/cpu/x86/lapic/lapic.c b/src/cpu/x86/lapic/lapic.c index 83a45b013c..f6cbe17992 100644 --- a/src/cpu/x86/lapic/lapic.c +++ b/src/cpu/x86/lapic/lapic.c @@ -17,9 +17,9 @@ void setup_lapic(void) /* Only Pentium Pro and later have those MSR stuff */ msr_t msr; - printk(BIOS_INFO, "Setting up local apic..."); + printk(BIOS_INFO, "Setting up local APIC..."); - /* Enable the local apic */ + /* Enable the local APIC */ msr = rdmsr(LAPIC_BASE_MSR); msr.lo |= LAPIC_BASE_MSR_ENABLE; msr.lo &= ~LAPIC_BASE_MSR_ADDR_MASK; @@ -32,7 +32,7 @@ void setup_lapic(void) lapic_write_around(LAPIC_TASKPRI, lapic_read_around(LAPIC_TASKPRI) & ~LAPIC_TPRI_MASK); - /* Put the local apic in virtual wire mode */ + /* Put the local APIC in virtual wire mode */ lapic_write_around(LAPIC_SPIV, (lapic_read_around(LAPIC_SPIV) & ~(LAPIC_VECTOR_MASK)) | LAPIC_SPIV_ENABLE); @@ -61,7 +61,7 @@ void setup_lapic(void) /* Only Pentium Pro and later have those MSR stuff */ msr_t msr; - printk(BIOS_INFO, "Disabling local apic..."); + printk(BIOS_INFO, "Disabling local APIC..."); msr = rdmsr(LAPIC_BASE_MSR); msr.lo &= ~LAPIC_BASE_MSR_ENABLE; diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index aaeceefe08..792ae7a8eb 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -165,7 +165,7 @@ static int lapic_start_cpu(unsigned long apicid) send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY; } while (send_status && (timeout++ < 1000)); if (timeout >= 1000) { - printk(BIOS_ERR, "CPU %ld: Second apic write timed out. " + printk(BIOS_ERR, "CPU %ld: Second APIC write timed out. " "Disabling\n", apicid); // too bad. return 0; @@ -546,7 +546,7 @@ void initialize_cpus(struct bus *cpu_bus) info = cpu_info(); #if NEED_LAPIC == 1 - /* Ensure the local apic is enabled */ + /* Ensure the local APIC is enabled */ enable_lapic(); /* Get the device path of the boot CPU */ |