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authorAaron Durbin <adurbin@chromium.org>2013-10-10 12:41:49 -0500
committerAaron Durbin <adurbin@google.com>2014-01-28 23:12:27 +0100
commit029aaf627c381a70b365e8b29797425785eb6788 (patch)
tree516c4147e7d0c18362b51afd0b200171bd4545ea /src/cpu/x86/lapic
parentf545abfd22a594ecb9c0678efa5278bb38a37a70 (diff)
downloadcoreboot-029aaf627c381a70b365e8b29797425785eb6788.tar.xz
x86: add common definitions for control registers
The access to control registers were scattered about. Provide a single header file to provide the correct access function and definitions. BUG=chrome-os-partner:22991 BRANCH=None TEST=Built and booted using this infrastructure. Also objdump'd the assembly to ensure consistency (objdump -d -r -S | grep xmm). Change-Id: Iff7a043e4e5ba930a6a77f968f1fcc14784214e9 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172641 Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/4873 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/cpu/x86/lapic')
-rw-r--r--src/cpu/x86/lapic/lapic_cpu_init.c27
1 files changed, 4 insertions, 23 deletions
diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c
index 555187fd7e..2aef2a4bcd 100644
--- a/src/cpu/x86/lapic/lapic_cpu_init.c
+++ b/src/cpu/x86/lapic/lapic_cpu_init.c
@@ -20,6 +20,7 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
+#include <cpu/x86/cr.h>
#include <cpu/x86/lapic.h>
#include <delay.h>
#include <lib.h>
@@ -401,26 +402,6 @@ void stop_this_cpu(void)
}
#endif
-#ifdef __SSE3__
-static __inline__ __attribute__((always_inline)) unsigned long readcr4(void)
-{
- unsigned long value;
- __asm__ __volatile__ (
- "mov %%cr4, %[value]"
- : [value] "=a" (value));
- return value;
-}
-
-static __inline__ __attribute__((always_inline)) void writecr4(unsigned long Data)
-{
- __asm__ __volatile__ (
- "mov %%eax, %%cr4"
- :
- : "a" (Data)
- );
-}
-#endif
-
/* C entry point of secondary cpus */
void asmlinkage secondary_cpu_init(unsigned int index)
{
@@ -435,9 +416,9 @@ void asmlinkage secondary_cpu_init(unsigned int index)
* Turn on CR4.OSFXSR and CR4.OSXMMEXCPT when SSE options enabled
*/
u32 cr4_val;
- cr4_val = readcr4();
- cr4_val |= (1 << 9 | 1 << 10);
- writecr4(cr4_val);
+ cr4_val = read_cr4();
+ cr4_val |= (CR4_OSFXSR | CR4_OSXMMEXCPT);
+ write_cr4(cr4_val);
#endif
cpu_initialize(index);
#if CONFIG_SERIAL_CPU_INIT