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| author | Alexandru Gagniuc <mr.nuke.me@gmail.com> | 2015-09-30 20:23:09 -0700 |
|---|---|---|
| committer | Alexandru Gagniuc <mr.nuke.me@gmail.com> | 2015-10-15 03:52:49 +0000 |
| commit | 86091f94b6ca58f4b8795503b274492d6a935c15 (patch) | |
| tree | db6e5f77dc57850b25574aed5063743ca4bc4d48 /src/cpu/x86/mp_init.c | |
| parent | 58562405c8c416a415652516b8af31b204b4ff0d (diff) | |
| download | coreboot-86091f94b6ca58f4b8795503b274492d6a935c15.tar.xz | |
cpu/mtrr.h: Fix macro names for MTRR registers
We use UNDERSCORE_CASE. For the MTRR macros that refer to an MSR,
we also remove the _MSR suffix, as they are, by definition, MSRs.
Change-Id: Id4483a75d62cf1b478a9105ee98a8f55140ce0ef
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11761
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/cpu/x86/mp_init.c')
| -rw-r--r-- | src/cpu/x86/mp_init.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 3c8450fd1d..c72cf0a434 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -179,10 +179,10 @@ static void setup_default_sipi_vector_params(struct sipi_params *sp) #define NUM_FIXED_MTRRS 11 static const unsigned int fixed_mtrrs[NUM_FIXED_MTRRS] = { - MTRRfix64K_00000_MSR, MTRRfix16K_80000_MSR, MTRRfix16K_A0000_MSR, - MTRRfix4K_C0000_MSR, MTRRfix4K_C8000_MSR, MTRRfix4K_D0000_MSR, - MTRRfix4K_D8000_MSR, MTRRfix4K_E0000_MSR, MTRRfix4K_E8000_MSR, - MTRRfix4K_F0000_MSR, MTRRfix4K_F8000_MSR, + MTRR_FIX_64K_00000, MTRR_FIX_16K_80000, MTRR_FIX_16K_A0000, + MTRR_FIX_4K_C0000, MTRR_FIX_4K_C8000, MTRR_FIX_4K_D0000, + MTRR_FIX_4K_D8000, MTRR_FIX_4K_E0000, MTRR_FIX_4K_E8000, + MTRR_FIX_4K_F0000, MTRR_FIX_4K_F8000, }; static inline struct saved_msr *save_msr(int index, struct saved_msr *entry) @@ -208,7 +208,7 @@ static int save_bsp_msrs(char *start, int size) msr_t msr; /* Determine number of MTRRs need to be saved. */ - msr = rdmsr(MTRRcap_MSR); + msr = rdmsr(MTRR_CAP_MSR); num_var_mtrrs = msr.lo & 0xff; /* 2 * num_var_mtrrs for base and mask. +1 for IA32_MTRR_DEF_TYPE. */ @@ -225,11 +225,11 @@ static int save_bsp_msrs(char *start, int size) } for (i = 0; i < num_var_mtrrs; i++) { - msr_entry = save_msr(MTRRphysBase_MSR(i), msr_entry); - msr_entry = save_msr(MTRRphysMask_MSR(i), msr_entry); + msr_entry = save_msr(MTRR_PHYS_BASE(i), msr_entry); + msr_entry = save_msr(MTRR_PHYS_MASK(i), msr_entry); } - msr_entry = save_msr(MTRRdefType_MSR, msr_entry); + msr_entry = save_msr(MTRR_DEF_TYPE_MSR, msr_entry); return msr_count; } |