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| author | Myles Watson <mylesgw@gmail.com> | 2009-10-16 16:32:57 +0000 |
|---|---|---|
| committer | Myles Watson <mylesgw@gmail.com> | 2009-10-16 16:32:57 +0000 |
| commit | 0f61a4fc98f135c0ed22c67ee3241bf5670a61e2 (patch) | |
| tree | b3867408477cdf8a3a2374f32d91b4f3936b7486 /src/cpu/x86/mtrr/earlymtrr.c | |
| parent | 9969bdc4fb3d36a39ed9efb67ef0bf638a4e8e09 (diff) | |
| download | coreboot-0f61a4fc98f135c0ed22c67ee3241bf5670a61e2.tar.xz | |
Change CONFIG_LB_MEM_TOPK to CONFIG_RAMTOP to match CONFIG_RAMBASE.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4788 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/x86/mtrr/earlymtrr.c')
| -rw-r--r-- | src/cpu/x86/mtrr/earlymtrr.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/cpu/x86/mtrr/earlymtrr.c b/src/cpu/x86/mtrr/earlymtrr.c index cff99b8964..ff37521957 100644 --- a/src/cpu/x86/mtrr/earlymtrr.c +++ b/src/cpu/x86/mtrr/earlymtrr.c @@ -11,8 +11,8 @@ #if defined(CONFIG_XIP_ROM_BASE) && !defined(CONFIG_XIP_ROM_SIZE) # error "CONFIG_XIP_ROM_BASE without CONFIG_XIP_ROM_SIZE" #endif -#if !defined(CONFIG_LB_MEM_TOPK) -# error "CONFIG_LB_MEM_TOPK not defined" +#if !defined(CONFIG_RAMTOP) +# error "CONFIG_RAMTOP not defined" #endif #if defined(CONFIG_XIP_ROM_SIZE) && ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE -1)) != 0) @@ -22,8 +22,8 @@ # error "CONFIG_XIP_ROM_BASE is not a multiple of CONFIG_XIP_ROM_SIZE" #endif -#if (CONFIG_LB_MEM_TOPK & (CONFIG_LB_MEM_TOPK -1)) != 0 -# error "CONFIG_LB_MEM_TOPK must be a power of 2" +#if (CONFIG_RAMTOP & (CONFIG_RAMTOP -1)) != 0 +# error "CONFIG_RAMTOP must be a power of 2" #endif static void disable_var_mtrr(unsigned reg) @@ -75,7 +75,7 @@ static void cache_lbmem(int type) { /* Enable caching for 0 - 1MB using variable mtrr */ disable_cache(); - set_var_mtrr(0, 0x00000000, CONFIG_LB_MEM_TOPK << 10, type); + set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, type); enable_cache(); } |