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| author | Aaron Durbin <adurbin@chromium.org> | 2013-04-24 20:59:43 -0500 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2013-05-01 07:12:17 +0200 |
| commit | bebf66909a11201a1bbfbdf7f1af40285d76a457 (patch) | |
| tree | ed037ab4d75d3f35aad545b16433c4219254c4f2 /src/cpu/x86/mtrr/mtrr.c | |
| parent | 243aa44b74935cfc969106dbbe2420ee4a2c39b2 (diff) | |
| download | coreboot-bebf66909a11201a1bbfbdf7f1af40285d76a457.tar.xz | |
x86: use boot state callbacks to disable rom cache
On x86 systems there is a concept of cachings the ROM. However,
the typical policy is that the boot cpu is the only one with
it enabled. In order to ensure the MTRRs are the same across cores
the rom cache needs to be disabled prior to OS resume or boot handoff.
Therefore, utilize the boot state callbacks to schedule the disabling
of the ROM cache at the ramstage exit points.
Change-Id: I4da5886d9f1cf4c6af2f09bb909f0d0f0faa4e62
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/3138
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/cpu/x86/mtrr/mtrr.c')
| -rw-r--r-- | src/cpu/x86/mtrr/mtrr.c | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index 608912754c..b69787bf4a 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -27,6 +27,7 @@ #include <stddef.h> #include <stdlib.h> #include <string.h> +#include <bootstate.h> #include <console/console.h> #include <device/device.h> #include <cpu/cpu.h> @@ -408,10 +409,17 @@ void x86_mtrr_disable_rom_caching(void) enable_cache(); } -void disable_cache_rom(void) +static void disable_cache_rom(void *unused) { x86_mtrr_disable_rom_caching(); } + +BOOT_STATE_INIT_ENTRIES(disable_rom_cache_bscb) = { + BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, + disable_cache_rom, NULL), + BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, + disable_cache_rom, NULL), +}; #endif struct var_mtrr_state { |