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authorPatrick Georgi <patrick@georgi-clan.de>2011-10-28 20:28:03 +0200
committerStefan Reinauer <stefan.reinauer@coreboot.org>2011-10-28 22:17:10 +0200
commit1da104647dc2828a6594bdc7b5ae119923dbcffa (patch)
tree3e4d1e8acc0e37bf0f5d93c4367d072c1629755b /src/cpu/x86/mtrr
parent0f8590f9ca8026af62efa510a1c717d2d0729e3d (diff)
downloadcoreboot-1da104647dc2828a6594bdc7b5ae119923dbcffa.tar.xz
Get rid of AUTO_XIP_ROM_BASE
That value is now generated from a code address and CONFIG_XIP_ROM_SIZE. This works as MTRRs are fully specified by their size and any address within the range. Change-Id: Id35d34eaf3be37f59cd2a968e3327d333ba71a34 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/348 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/cpu/x86/mtrr')
-rw-r--r--src/cpu/x86/mtrr/earlymtrr.c7
1 files changed, 6 insertions, 1 deletions
diff --git a/src/cpu/x86/mtrr/earlymtrr.c b/src/cpu/x86/mtrr/earlymtrr.c
index dcfcccd0f3..f8119d3e59 100644
--- a/src/cpu/x86/mtrr/earlymtrr.c
+++ b/src/cpu/x86/mtrr/earlymtrr.c
@@ -29,6 +29,8 @@ static void cache_lbmem(int type)
enable_cache();
}
+const int addr_det = 0;
+
/* the fixed and variable MTTRs are power-up with random values,
* clear them to MTRR_TYPE_UNCACHEABLE for safty.
*/
@@ -52,8 +54,11 @@ static void do_early_mtrr_init(const unsigned long *mtrr_msrs)
#if defined(CONFIG_XIP_ROM_SIZE)
/* enable write through caching so we can do execute in place
* on the flash rom.
+ * Determine address by calculating the XIP_ROM_SIZE sized area with
+ * XIP_ROM_SIZE alignment that contains the global variable defined above;
*/
- set_var_mtrr(1, REAL_XIP_ROM_BASE, CONFIG_XIP_ROM_SIZE, MTRR_TYPE_WRBACK);
+ unsigned long f = (unsigned long)&addr_det & ~(CONFIG_XIP_ROM_SIZE - 1);
+ set_var_mtrr(1, f, CONFIG_XIP_ROM_SIZE, MTRR_TYPE_WRBACK);
#endif
/* Set the default memory type and enable fixed and variable MTRRs