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authorMartin Roth <martin.roth@se-eng.com>2013-07-08 16:23:54 -0600
committerStefan Reinauer <stefan.reinauer@coreboot.org>2013-07-11 22:36:59 +0200
commit4c3ab7376ebb2e3e18919f1ab663d317dfec9b9c (patch)
tree6bd8440a05f6ea1184c0a5500d43cc92ab683f01 /src/cpu/x86/mtrr
parent0cb07e3476d9408d0935253f9f26c0a8ddc28401 (diff)
downloadcoreboot-4c3ab7376ebb2e3e18919f1ab663d317dfec9b9c.tar.xz
cpu: Fix spelling
Change-Id: I69c46648de0689e9bed84c7726906024ad65e769 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/3729 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/cpu/x86/mtrr')
-rw-r--r--src/cpu/x86/mtrr/earlymtrr.c4
-rw-r--r--src/cpu/x86/mtrr/mtrr.c18
2 files changed, 11 insertions, 11 deletions
diff --git a/src/cpu/x86/mtrr/earlymtrr.c b/src/cpu/x86/mtrr/earlymtrr.c
index 55dbd2f4a4..f16da279c6 100644
--- a/src/cpu/x86/mtrr/earlymtrr.c
+++ b/src/cpu/x86/mtrr/earlymtrr.c
@@ -32,7 +32,7 @@ static void cache_ramstage(void)
const int addr_det = 0;
/* the fixed and variable MTTRs are power-up with random values,
- * clear them to MTRR_TYPE_UNCACHEABLE for safty.
+ * clear them to MTRR_TYPE_UNCACHEABLE for safety.
*/
static void do_early_mtrr_init(const unsigned long *mtrr_msrs)
{
@@ -43,7 +43,7 @@ static void do_early_mtrr_init(const unsigned long *mtrr_msrs)
msr_t msr;
const unsigned long *msr_addr;
- /* Inialize all of the relevant msrs to 0 */
+ /* Initialize all of the relevant msrs to 0 */
msr.lo = 0;
msr.hi = 0;
unsigned long msr_nr;
diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c
index b69787bf4a..8f1c35ec6e 100644
--- a/src/cpu/x86/mtrr/mtrr.c
+++ b/src/cpu/x86/mtrr/mtrr.c
@@ -94,7 +94,7 @@ static inline unsigned int fms(unsigned int x)
return r;
}
-/* fls: find least sigificant bit set */
+/* fls: find least significant bit set */
static inline unsigned int fls(unsigned int x)
{
int r;
@@ -160,8 +160,8 @@ static struct memranges *get_physical_address_space(void)
static struct memranges addr_space_storage;
/* In order to handle some chipsets not being able to pre-determine
- * uncacheable ranges, such as graphics memory, at resource inseration
- * time remove unacheable regions from the cacheable ones. */
+ * uncacheable ranges, such as graphics memory, at resource insertion
+ * time remove uncacheable regions from the cacheable ones. */
if (addr_space == NULL) {
struct range_entry *r;
unsigned long mask;
@@ -216,7 +216,7 @@ static struct memranges *get_physical_address_space(void)
}
/* Fixed MTRR descriptor. This structure defines the step size and begin
- * and end (exclusive) address covered by a set of fixe MTRR MSRs.
+ * and end (exclusive) address covered by a set of fixed MTRR MSRs.
* It also describes the offset in byte intervals to store the calculated MTRR
* type in an array. */
struct fixed_mtrr_desc {
@@ -533,7 +533,7 @@ static void calc_var_mtrrs_with_hole(struct var_mtrr_state *var_state,
struct range_entry *next;
/*
- * Determine MTRRs based on the following algoirthm for the given entry:
+ * Determine MTRRs based on the following algorithm for the given entry:
* +------------------+ b2 = ALIGN_UP(end)
* | 0 or more bytes | <-- hole is carved out between b1 and b2
* +------------------+ a2 = b1 = end
@@ -571,7 +571,7 @@ static void calc_var_mtrrs_with_hole(struct var_mtrr_state *var_state,
b1 = a2;
- /* First check if a1 is >= 4GiB and the current etnry is the last
+ /* First check if a1 is >= 4GiB and the current entry is the last
* entry. If so perform an optimization of covering a larger range
* defined by the base address' alignment. */
if (a1 >= RANGE_4GB && next == NULL) {
@@ -686,10 +686,10 @@ static int calc_var_mtrrs(struct memranges *addr_space,
* 1. UC as default type with no holes at top of range.
* 2. UC as default using holes at top of range.
* 3. WB as default.
- * The lowest count is then used as default after totalling all
- * MTRRs. Note that the optimal algoirthm for UC default is marked in
+ * The lowest count is then used as default after totaling all
+ * MTRRs. Note that the optimal algorithm for UC default is marked in
* the tag of each range regardless of final decision. UC takes
- * precedence in the MTRR archiecture. Therefore, only holes can be
+ * precedence in the MTRR architecture. Therefore, only holes can be
* used when the type of the region is MTRR_TYPE_WRBACK with
* MTRR_TYPE_UNCACHEABLE as the default type.
*/