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authorsselvar2 <susendra.selvaraj@intel.com>2016-06-09 21:06:34 +0530
committerMartin Roth <martinroth@google.com>2016-07-22 18:59:36 +0200
commit9d29c3cc3182c8e8f38b3a2b1e0d445cdbd448bc (patch)
tree8ac3317c525f7988ef493509d568dacc4fdf0e30 /src/cpu/x86/mtrr
parentdf7ad448539fa68138b7439de1e4981e9f6801c5 (diff)
downloadcoreboot-9d29c3cc3182c8e8f38b3a2b1e0d445cdbd448bc.tar.xz
intel/amenia: Write protect GPIO relative to bank offset
Update the write protect GPIO reported in ACPI to GPIO_75. Also update the controller ID to "INT3452:01" which will point at the goldmont device and includes write protect GPIO. BUG=none BRANCH=none TEST=verify crossystem output for wpsw_cur. Change-Id: Id6b172e289976072836746c1814e0300544a06cb Signed-off-by: sselvar2 <susendra.selvaraj@intel.com> Reviewed-on: https://coreboot.intel.com/7771 Reviewed-by: Sparry, Icarus W <icarus.w.sparry@intel.com> Reviewed-by: Petrov, Andrey <andrey.petrov@intel.com> Tested-by: Petrov, Andrey <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15496 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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