diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2013-03-26 14:10:34 -0500 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2013-03-29 19:57:31 +0100 |
| commit | 9b027fe5b028011593c98d2af8727199b74d3e4c (patch) | |
| tree | 2472d6133bb69dcf871b03bb9c90160aee756966 /src/cpu/x86/mtrr | |
| parent | a05a8522ce1dd90c6d667b70bafb24757a27c656 (diff) | |
| download | coreboot-9b027fe5b028011593c98d2af8727199b74d3e4c.tar.xz | |
mtrr: honor IORESOURCE_WRCOMB
All resources that set the IORESOURCE_WRCOMB attribute which are
also marked as IORESOURCE_PREFETCH will have a MTRR set up that
is of the write-combining cacheable type. The only resources on
x86 that can be set to write-combining are prefetchable ones.
Change-Id: Iba7452cff3677e07d7e263b79982a49c93be9c54
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2892
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/cpu/x86/mtrr')
| -rw-r--r-- | src/cpu/x86/mtrr/mtrr.c | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index 81ea6da91d..74aae64a89 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -142,10 +142,12 @@ static struct memranges *get_physical_address_space(void) * time remove unacheable regions from the cacheable ones. */ if (addr_space == NULL) { struct range_entry *r; - const unsigned long mask = IORESOURCE_CACHEABLE; + unsigned long mask; + unsigned long match; addr_space = &addr_space_storage; + mask = IORESOURCE_CACHEABLE; /* Collect cacheable and uncacheable address ranges. The * uncacheable regions take precedence over the cacheable * regions. */ @@ -153,6 +155,14 @@ static struct memranges *get_physical_address_space(void) memranges_add_resources(addr_space, mask, 0, MTRR_TYPE_UNCACHEABLE); + /* Handle any write combining resources. Only prefetchable + * resources with the IORESOURCE_WRCOMB flag are appropriate + * for this MTRR type. */ + match = IORESOURCE_PREFETCH | IORESOURCE_WRCOMB; + mask |= match; + memranges_add_resources(addr_space, mask, match, + MTRR_TYPE_WRCOMB); + /* The address space below 4GiB is special. It needs to be * covered entirly by range entries so that MTRR calculations * can be properly done for the full 32-bit address space. |