diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2013-03-26 13:09:39 -0500 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2013-03-29 20:09:36 +0100 |
| commit | bc07f5d93552640793254ce003937ec646120a21 (patch) | |
| tree | 091f2189c38629d64579c5864220f8b2f2039db0 /src/cpu/x86/mtrr | |
| parent | f567f16af4c3cbfcadc3bc5c44b569a592829262 (diff) | |
| download | coreboot-bc07f5d93552640793254ce003937ec646120a21.tar.xz | |
x86: add rom cache variable MTRR index to tables
Downstream payloads may need to take advantage of caching the
ROM for performance reasons. Add the ability to communicate the
variable range MTRR index to use to perform the caching enablement.
An example usage implementation would be to obtain the variable MTRR
index that covers the ROM from the coreboot tables. Then one would
disable caching and change the MTRR type from uncacheable to
write-protect and enable caching. The opposite sequence is required
to tearn down the caching.
Change-Id: I4d486cfb986629247ab2da7818486973c6720ef5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2919
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/cpu/x86/mtrr')
| -rw-r--r-- | src/cpu/x86/mtrr/mtrr.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index dad10292a9..9c8f8c7647 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -349,6 +349,11 @@ void x86_setup_fixed_mtrrs(void) #if CONFIG_CACHE_ROM static long rom_cache_mtrr = -1; +long x86_mtrr_rom_cache_var_index(void) +{ + return rom_cache_mtrr; +} + void x86_mtrr_enable_rom_caching(void) { msr_t msr_val; |