diff options
| author | Kevin O'Connor <kevin@koconnor.net> | 2011-01-19 06:32:35 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2011-01-19 06:32:35 +0000 |
| commit | 5bb9fd6e4dae32f86a07676228034d3828820037 (patch) | |
| tree | 9933b8327f3af0ce6814d5402ce798a3720d273e /src/cpu/x86/mtrr | |
| parent | 4adc9eb60047e7dc3a7921793c489fff4fe3fc57 (diff) | |
| download | coreboot-5bb9fd6e4dae32f86a07676228034d3828820037.tar.xz | |
Now that the VIA code is run above 1Meg (like other boards), it should
cache that range instead of the first 1Meg. This reduces boot time by
about 1 second on epia-cn.
This patch also adds a MTRRphysMaskValid bit definition.
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6272 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/x86/mtrr')
| -rw-r--r-- | src/cpu/x86/mtrr/mtrr.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index 734734a77b..8e7beea76e 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -62,7 +62,7 @@ static void enable_var_mtrr(void) msr_t msr; msr = rdmsr(MTRRdefType_MSR); - msr.lo |= 0x800; + msr.lo |= MTRRdefTypeEn; wrmsr(MTRRdefType_MSR, msr); } @@ -115,7 +115,7 @@ static void set_var_mtrr( /* Bit 32-35 of MTRRphysMask should be set to 1 */ base.lo |= type; - mask.lo |= 0x800; + mask.lo |= MTRRphysMaskValid; wrmsr (MTRRphysBase_MSR(reg), base); wrmsr (MTRRphysMask_MSR(reg), mask); |