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authorSubrata Banik <subrata.banik@intel.com>2019-08-07 08:54:15 +0530
committerSubrata Banik <subrata.banik@intel.com>2019-08-08 04:57:09 +0000
commit6c8a040ec5e52a2032055c0e59dd68a8851d4bbc (patch)
tree086f08e0c1d0d5e625a5ca4d8e8a171a70ebda42 /src/cpu/x86/mtrr
parent41d9b651491be2b6e0e144a2aaf3051f72863f13 (diff)
downloadcoreboot-6c8a040ec5e52a2032055c0e59dd68a8851d4bbc.tar.xz
cpu/x86/mtrr: Replace CONFIG_CPU_ADDR_BITS with cpu_phys_address_size()
This patch helps to generate correct MTRR mask value while using set_var_mtrr(). example: set_var_mtrr(1, 0x99000000, 16*MiB, WP) without CL : 0x0000000099000005: PHYBASE2: Address = 0x0000000099000000, WP 0x0000000fff000800: PHYMASK2: Length = 0x0000007001000000, Valid with CL : 0x0000000099000005: PHYBASE1: Address = 0x0000000099000000, WP 0x0000007fff000800: PHYMASK1: Length = 0x0000000001000000, Valid Change-Id: Ie3185dd8d4af73ec0605e19e9aa4223f2c2ad462 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34753 Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu/x86/mtrr')
-rw-r--r--src/cpu/x86/mtrr/earlymtrr.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/cpu/x86/mtrr/earlymtrr.c b/src/cpu/x86/mtrr/earlymtrr.c
index 02ad85f321..5d7ff2cf45 100644
--- a/src/cpu/x86/mtrr/earlymtrr.c
+++ b/src/cpu/x86/mtrr/earlymtrr.c
@@ -11,6 +11,7 @@
* GNU General Public License for more details.
*/
+#include <cpu/cpu.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/msr.h>
@@ -51,6 +52,6 @@ void set_var_mtrr(
basem.hi = 0;
wrmsr(MTRR_PHYS_BASE(reg), basem);
maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID;
- maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1;
+ maskm.hi = (1 << (cpu_phys_address_size() - 32)) - 1;
wrmsr(MTRR_PHYS_MASK(reg), maskm);
}