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| author | Barnali Sarkar <barnali.sarkar@intel.com> | 2016-08-03 12:15:22 +0530 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-08-08 18:24:04 +0200 |
| commit | 8f2f22d25806a4547be1a1a125f153bb4b0fe581 (patch) | |
| tree | 959268d99a149b80ec4d4dde38ec5da63a3749f6 /src/cpu/x86/pae | |
| parent | 0dddcd76d74274715b0472ca41ddac88a5203b84 (diff) | |
| download | coreboot-8f2f22d25806a4547be1a1a125f153bb4b0fe581.tar.xz | |
skylake/devicetree: Add PIRQ Routing programming
Program PIRQ Routing with correct values, as done by FSP, and also in
'soc/intel/skylake/romstage/pch.c' file. If not done, these values get
overridden by "0" during PxRC -> PIRQ programming in ramstage, in
'soc/intel/skylake/lpc.c' file pch_pirq_init()function.
BUG=none
BRANCH=none
TEST=Build and boot kunimitsu
Change-Id: Ibeb9a64824a71c253e45d6a1c6088abd737cf046
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/16044
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Diffstat (limited to 'src/cpu/x86/pae')
0 files changed, 0 insertions, 0 deletions