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authorAaron Durbin <adurbin@chromium.org>2012-12-21 21:21:48 -0600
committerRonald G. Minnich <rminnich@gmail.com>2013-03-18 17:07:50 +0100
commit29ffa54969414b833de5c61b507b061f920d650b (patch)
treee359cc2f27216e9d10e980cce2a2d7c0745729e5 /src/cpu/x86/smm/smmrelocate.S
parentb7ecf6d83047e70ed5846ac35833a04983318b9c (diff)
downloadcoreboot-29ffa54969414b833de5c61b507b061f920d650b.tar.xz
haswell: Use SMM Modules
This commit adds support for using the SMM modules for haswell-based boards. The SMI handling was also refactored to put the relocation handler and permanent SMM handler loading in the cpu directory. All tseg adjustment support is dropped by relying on the SMM module support to perform the necessary relocations. Change-Id: I8dd23610772fc4408567d9f4adf339596eac7b1f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2728 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/cpu/x86/smm/smmrelocate.S')
-rw-r--r--src/cpu/x86/smm/smmrelocate.S5
1 files changed, 0 insertions, 5 deletions
diff --git a/src/cpu/x86/smm/smmrelocate.S b/src/cpu/x86/smm/smmrelocate.S
index a6379ccc00..16d4b9fde0 100644
--- a/src/cpu/x86/smm/smmrelocate.S
+++ b/src/cpu/x86/smm/smmrelocate.S
@@ -39,8 +39,6 @@
#include "../../../southbridge/intel/bd82x6x/pch.h"
#elif CONFIG_SOUTHBRIDGE_INTEL_I82801IX
#include "../../../southbridge/intel/i82801ix/i82801ix.h"
-#elif CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT
-#include "../../../southbridge/intel/lynxpoint/pch.h"
#else
#error "Southbridge needs SMM handler support."
#endif
@@ -50,9 +48,6 @@
#if CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE
#include <northbridge/intel/sandybridge/sandybridge.h>
#define TSEG_BAR (DEFAULT_PCIEXBAR | TSEG)
-#elif CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT
-#include <northbridge/intel/haswell/haswell.h>
-#define TSEG_BAR (DEFAULT_PCIEXBAR | TSEG)
#else
#error "Northbridge must define TSEG_BAR."
#endif