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| author | Aaron Durbin <adurbin@chromium.org> | 2015-03-29 22:16:55 -0500 |
|---|---|---|
| committer | Aaron Durbin <adurbin@google.com> | 2015-03-30 23:03:27 +0200 |
| commit | e73dae4bf590c6ad054f0d736b82089fd65a6c0d (patch) | |
| tree | d1453053dc825f8ee5992ec7535bfcfeca781ad2 /src/cpu/x86/smm | |
| parent | 83a8df52b049e9d6f09a8fca6b58dc080c2865cd (diff) | |
| download | coreboot-e73dae4bf590c6ad054f0d736b82089fd65a6c0d.tar.xz | |
x86: fix SMM programs linked with gc-sections
Commit f69a99db (coreboot: x86: enable gc-sections) added
gc-sections to the linker command line. The SMM-specific
linker scripts were not interrogated to see if all the
sections were being included properly. .data, .bss, and .sbss
did not have the proper globs set to put the SMM programs in
the expected order.
Lastly, explicitly set the ENTRY for the SMM programs.
Change-Id: Ibb579d18d4819af666d6ec7dfc30776e8c404b71
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9160
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/cpu/x86/smm')
| -rw-r--r-- | src/cpu/x86/smm/smm.ld | 4 | ||||
| -rw-r--r-- | src/cpu/x86/smm/smm_tseg.ld | 4 | ||||
| -rw-r--r-- | src/cpu/x86/smm/smmhandler.S | 1 | ||||
| -rw-r--r-- | src/cpu/x86/smm/smmhandler_tseg.S | 1 |
4 files changed, 10 insertions, 0 deletions
diff --git a/src/cpu/x86/smm/smm.ld b/src/cpu/x86/smm/smm.ld index 5d316a8f4d..c1981610b8 100644 --- a/src/cpu/x86/smm/smm.ld +++ b/src/cpu/x86/smm/smm.ld @@ -1,6 +1,7 @@ /* Maximum number of CPUs/cores */ CPUS = 4; +ENTRY(smm_handler_start); SECTIONS { @@ -25,11 +26,14 @@ SECTIONS /* C read-write data of the SMM handler */ . = ALIGN(4); *(.data) + *(.data.*) /* C uninitialized data of the SMM handler */ . = ALIGN(4); *(.bss) + *(.bss.*) *(.sbss) + *(.sbss.*) /* What is this? */ *(COMMON) diff --git a/src/cpu/x86/smm/smm_tseg.ld b/src/cpu/x86/smm/smm_tseg.ld index 99f2aa0a67..b57461caa0 100644 --- a/src/cpu/x86/smm/smm_tseg.ld +++ b/src/cpu/x86/smm/smm_tseg.ld @@ -1,5 +1,6 @@ /* Maximum number of CPUs/cores */ CPUS = 16; +ENTRY(smm_handler_start); SECTIONS { @@ -52,11 +53,14 @@ SECTIONS /* C read-write data of the SMM handler */ . = ALIGN(4); *(.data) + *(.data.*) /* C uninitialized data of the SMM handler */ . = ALIGN(4); *(.bss) + *(.bss.*) *(.sbss) + *(.sbss.*) *(COMMON) . = ALIGN(4); diff --git a/src/cpu/x86/smm/smmhandler.S b/src/cpu/x86/smm/smmhandler.S index 5d3aae3701..611c0f3fa3 100644 --- a/src/cpu/x86/smm/smmhandler.S +++ b/src/cpu/x86/smm/smmhandler.S @@ -75,6 +75,7 @@ * * All the bad magic is not all that bad after all. */ +.global smm_handler_start smm_handler_start: movw $(smm_gdtptr16 - smm_handler_start + SMM_HANDLER_OFFSET), %bx data32 lgdt %cs:(%bx) diff --git a/src/cpu/x86/smm/smmhandler_tseg.S b/src/cpu/x86/smm/smmhandler_tseg.S index c9d78b9dce..ee8bd26468 100644 --- a/src/cpu/x86/smm/smmhandler_tseg.S +++ b/src/cpu/x86/smm/smmhandler_tseg.S @@ -91,6 +91,7 @@ * * All the bad magic is not all that bad after all. */ +.global smm_handler_start smm_handler_start: movl $(TSEG_BAR), %eax /* Get TSEG base from PCIE */ addr32 movl (%eax), %edx /* Save TSEG_BAR in %edx */ |