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| author | Aaron Durbin <adurbin@chromium.org> | 2016-08-11 14:40:09 -0500 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-08-18 22:04:34 +0200 |
| commit | 08e842c0d10c69b8fc07f6b00ea4dbeb85ac6e58 (patch) | |
| tree | 862eae8b485ccb5c72fadeb422ac98df26ecb3bf /src/cpu/x86/sse_enable.inc | |
| parent | 240853bf25cbff39f0099dd6ed3fe0bfa75c9d0c (diff) | |
| download | coreboot-08e842c0d10c69b8fc07f6b00ea4dbeb85ac6e58.tar.xz | |
Kconfig: rename BOOT_MEDIA_SPI_BUS to BOOT_DEVICE_SPI_FLASH_BUS
Provide a default value of 0 in drivers/spi as there weren't
default values aside from specific mainboards and arch/x86.
Remove any default 0 values while noting to keep the option's
default to 0.
BUG=chrome-os-partner:56151
Change-Id: If9ef585e011a46b5cd152a03e41d545b36355a61
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16192
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/cpu/x86/sse_enable.inc')
0 files changed, 0 insertions, 0 deletions