summaryrefslogtreecommitdiff
path: root/src/cpu/x86/tsc
diff options
context:
space:
mode:
authorPatrick Georgi <patrick.georgi@coresystems.de>2010-09-08 10:58:02 +0000
committerPatrick Georgi <patrick.georgi@coresystems.de>2010-09-08 10:58:02 +0000
commita4c0a1d6e6669736e101ada54b81d529f7c84cde (patch)
tree14fadad764d9d21dc9aa7b65ce270d8705e5121f /src/cpu/x86/tsc
parent24f83a76ae2608f7df0a11d80537fdc907f1e88c (diff)
downloadcoreboot-a4c0a1d6e6669736e101ada54b81d529f7c84cde.tar.xz
Make timer2 the default choice for TSC initialization.
For boards where timer2 is unusable, there's still the IO based initialization available using the Kconfig option TSC_CALIBRATE_WITH_IO Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Kevin O'Connor <kevin@koconnor.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5787 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/x86/tsc')
-rw-r--r--src/cpu/x86/tsc/delay_tsc.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/cpu/x86/tsc/delay_tsc.c b/src/cpu/x86/tsc/delay_tsc.c
index 1127867638..a77a61c774 100644
--- a/src/cpu/x86/tsc/delay_tsc.c
+++ b/src/cpu/x86/tsc/delay_tsc.c
@@ -7,7 +7,7 @@
static unsigned long clocks_per_usec;
-#if (CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 == 1)
+#if !CONFIG_TSC_CALIBRATE_WITH_IO
#define CLOCK_TICK_RATE 1193180U /* Underlying HZ */
/* ------ Calibrate the TSC -------
@@ -82,7 +82,7 @@ bad_ctc:
return 0;
}
-#else /* CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 */
+#else /* CONFIG_TSC_CALIBRATE_WITH_IO */
/*
* this is the "no timer2" version.