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authorEdward O'Callaghan <eocallaghan@alterapraxis.com>2014-07-16 19:03:55 +1000
committerEdward O'Callaghan <eocallaghan@alterapraxis.com>2014-07-17 02:20:12 +0200
commitdc112e3515647f17b92ce5205041e03dd53096ef (patch)
tree3479298f7e1479f65521e2762fe53a261b4c6d29 /src/cpu/x86/tsc
parent29794b7ad744ea8b2a8b91e2e31a90c599971f5b (diff)
downloadcoreboot-dc112e3515647f17b92ce5205041e03dd53096ef.tar.xz
cpu,Makefile.inc: Trivial - drop trailing blank lines at EOF
Change-Id: I7e8866d76d7f286e10160d7dc4f21f01a913bfee Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6286 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Diffstat (limited to 'src/cpu/x86/tsc')
-rw-r--r--src/cpu/x86/tsc/Makefile.inc1
1 files changed, 0 insertions, 1 deletions
diff --git a/src/cpu/x86/tsc/Makefile.inc b/src/cpu/x86/tsc/Makefile.inc
index 3bbae847f8..600f3131b7 100644
--- a/src/cpu/x86/tsc/Makefile.inc
+++ b/src/cpu/x86/tsc/Makefile.inc
@@ -3,4 +3,3 @@ romstage-$(CONFIG_TSC_CONSTANT_RATE) += delay_tsc.c
ifeq ($(CONFIG_HAVE_SMI_HANDLER),y)
smm-$(CONFIG_TSC_CONSTANT_RATE) += delay_tsc.c
endif
-