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| author | Andrey Petrov <andrey.petrov@intel.com> | 2016-04-23 12:31:01 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-04-28 05:45:37 +0200 |
| commit | 0c85b7f4d7180c9307fd95bb887791d4231397a5 (patch) | |
| tree | 0caa24e1c6b2d70b8d184337e9cc891b58fd10ea /src/cpu/x86 | |
| parent | e976bd44692d2adb320a1256f1b6bfaa6469108a (diff) | |
| download | coreboot-0c85b7f4d7180c9307fd95bb887791d4231397a5.tar.xz | |
soc/intel/apollolake: Add cache for BIOS ROM
Enable caching of BIOS region with variable MTRR. This is most
useful if enabled early such as in bootblock.
Change-Id: I39f33ca43f06fce26d1d48e706c97f097e3c10f1
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/14480
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/cpu/x86')
| -rw-r--r-- | src/cpu/x86/mtrr/Makefile.inc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/cpu/x86/mtrr/Makefile.inc b/src/cpu/x86/mtrr/Makefile.inc index 9b7207b9e0..e6e9c50bc2 100644 --- a/src/cpu/x86/mtrr/Makefile.inc +++ b/src/cpu/x86/mtrr/Makefile.inc @@ -1,2 +1,3 @@ ramstage-y += mtrr.c romstage-y += earlymtrr.c +bootblock-y += earlymtrr.c |