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authorAaron Durbin <adurbin@chromium.org>2016-04-08 19:51:22 -0500
committerMartin Roth <martinroth@google.com>2016-04-11 16:12:06 +0200
commit6f3a55ae7ec2b2d8b55a09e4eec3377084339800 (patch)
treef8efba1e7e9af7a9bda697df0758e01f873e313e /src/cpu/x86
parentb2229dc1997b22d6497ebc1664b2c710584e8117 (diff)
downloadcoreboot-6f3a55ae7ec2b2d8b55a09e4eec3377084339800.tar.xz
src/cpu/x86: remove TSC_CALIBRATE_WITH_IO
It's not selected by any path so it's a dead option with associated dead code. Remove the config option as well as the code paths that were never used any longer. Change-Id: Ie536eee54e5c63bd90192f413c69e0dd2fea9171 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14299 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Myles Watson <mylesgw@gmail.com>
Diffstat (limited to 'src/cpu/x86')
-rw-r--r--src/cpu/x86/Kconfig6
-rw-r--r--src/cpu/x86/tsc/delay_tsc.c58
2 files changed, 0 insertions, 64 deletions
diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig
index d8f338d5d0..6cd65cc490 100644
--- a/src/cpu/x86/Kconfig
+++ b/src/cpu/x86/Kconfig
@@ -49,12 +49,6 @@ config TSC_MONOTONIC_TIMER
Expose monotonic time using the TSC.
# This option is used in code but never selected.
-config TSC_CALIBRATE_WITH_IO
- bool
- depends on UDELAY_TSC
- default n
-
-# This option is used in code but never selected.
config UDELAY_TIMER2
bool
default n
diff --git a/src/cpu/x86/tsc/delay_tsc.c b/src/cpu/x86/tsc/delay_tsc.c
index 0ad5d3bbdf..9441622ce3 100644
--- a/src/cpu/x86/tsc/delay_tsc.c
+++ b/src/cpu/x86/tsc/delay_tsc.c
@@ -16,7 +16,6 @@ static unsigned long calibrate_tsc(void)
return tsc_freq_mhz();
}
#else /* CONFIG_TSC_CONSTANT_RATE */
-#if !CONFIG_TSC_CALIBRATE_WITH_IO
#define CLOCK_TICK_RATE 1193180U /* Underlying HZ */
/* ------ Calibrate the TSC -------
@@ -91,63 +90,6 @@ bad_ctc:
return 0;
}
-#else /* CONFIG_TSC_CALIBRATE_WITH_IO */
-
-/*
- * this is the "no timer2" version.
- * to calibrate tsc, we get a TSC reading, then do 1,000,000 outbs to port 0x80
- * then we read TSC again, and divide the difference by 1,000,000
- * we have found on a wide range of machines that this gives us a a
- * good microsecond value
- * to +- 10%. On a dual AMD 1.6 Ghz box, it gives us .97 microseconds, and on a
- * 267 Mhz. p5, it gives us 1.1 microseconds.
- * also, since gcc now supports long long, we use that.
- * also no unsigned long long / operator, so we play games.
- * about the only thing you can do with long longs, it seems,
- *is return them and assign them.
- * (and do asm on them, yuck)
- * so avoid all ops on long longs.
- */
-static unsigned long long calibrate_tsc(void)
-{
- unsigned long long start, end, delta;
- unsigned long result, count;
-
- printk(BIOS_SPEW, "Calibrating delay loop...\n");
- start = rdtscll();
- // no udivdi3 because we don't like libgcc. (only in x86emu)
- // so we count to 1<< 20 and then right shift 20
- for(count = 0; count < (1<<20); count ++)
- inb(0x80);
- end = rdtscll();
-
-#if 0
- // make delta be (endhigh - starthigh) + (endlow - startlow)
- // but >> 20
- // do it this way to avoid gcc warnings.
- start = tsc_start.hi;
- start <<= 32;
- start |= start.lo;
- end = tsc_end.hi;
- end <<= 32;
- end |= tsc_end.lo;
-#endif
- delta = end - start;
- // at this point we have a delta for 1,000,000 outbs. Now rescale for one microsecond.
- delta >>= 20;
- // save this for microsecond timing.
- result = delta;
- printk(BIOS_SPEW, "end %llx, start %llx\n", end, start);
- printk(BIOS_SPEW, "32-bit delta %ld\n", (unsigned long) delta);
-
- printk(BIOS_SPEW, "%s 32-bit result is %ld\n",
- __func__,
- result);
- return delta;
-}
-
-
-#endif /* CONFIG_TSC_CALIBRATE_WITH_IO */
#endif /* CONFIG_TSC_CONSTANT_RATE */
void init_timer(void)