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authorRonald G. Minnich <rminnich@gmail.com>2013-07-22 20:17:18 +0200
committerRonald G. Minnich <rminnich@gmail.com>2013-07-22 20:46:51 +0200
commitb5e777c433642950fbe6e907a234995ed7f34b8d (patch)
treea8abdfea9064d8c16c095878a1ea9020c0426e28 /src/cpu/x86
parent4c2ebeba78e437df2d156a4c68f1fb15b62926f5 (diff)
downloadcoreboot-b5e777c433642950fbe6e907a234995ed7f34b8d.tar.xz
X86: make the SIPI num_starts a config variable
The code to figure out how to set num_starts was starting to get kludgy. It's a constant for a given CPU; constants should be constant; make it a config variable. This change includes an example of how to override it. Build but not boot tested; drivers welcome. Change-Id: Iddd906a707bb16251615c7b42f2bfb5a044379b4 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/3796 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Diffstat (limited to 'src/cpu/x86')
-rw-r--r--src/cpu/x86/lapic/lapic_cpu_init.c12
1 files changed, 3 insertions, 9 deletions
diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c
index a3bab4658a..cd092805b7 100644
--- a/src/cpu/x86/lapic/lapic_cpu_init.c
+++ b/src/cpu/x86/lapic/lapic_cpu_init.c
@@ -101,7 +101,7 @@ static int lapic_start_cpu(unsigned long apicid)
{
int timeout;
unsigned long send_status, accept_status;
- int j, num_starts, maxlvt;
+ int j, maxlvt;
/*
* Starting actual IPI sequence...
@@ -167,20 +167,14 @@ static int lapic_start_cpu(unsigned long apicid)
return 0;
}
-#if !CONFIG_CPU_AMD_MODEL_10XXX
- num_starts = 2;
-#else
- num_starts = 1;
-#endif
-
/*
* Run STARTUP IPI loop.
*/
- printk(BIOS_SPEW, "#startup loops: %d.\n", num_starts);
+ printk(BIOS_SPEW, "#startup loops: %d.\n", CONFIG_NUM_IPI_STARTS);
maxlvt = 4;
- for (j = 1; j <= num_starts; j++) {
+ for (j = 1; j <= CONFIG_NUM_IPI_STARTS; j++) {
printk(BIOS_SPEW, "Sending STARTUP #%d to %lu.\n", j, apicid);
lapic_read_around(LAPIC_SPIV);
lapic_write(LAPIC_ESR, 0);