AMD Rev F support

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2435 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

5 files changed, 56 insertions, 23 deletions

diff --git a/src/cpu/x86/car/copy_and_run.c b/src/cpu/x86/car/copy_and_run.c
index 5c61177a10..4000a09e18 100644
--- a/src/cpu/x86/car/copy_and_run.c
+++ b/src/cpu/x86/car/copy_and_run.c
@@ -44,7 +44,7 @@ static void copy_and_run(unsigned cpu_reset)
 	
 //	dump_mem(src, src+0x100);
 
-	olen=unrv2b(src, dst);
+	olen = unrv2b(src, dst, &ilen);
 
 #endif
 //	dump_mem(dst, dst+0x100);
diff --git a/src/cpu/x86/lapic/lapic.c b/src/cpu/x86/lapic/lapic.c
index 8282890bf7..8c111e8d71 100644
--- a/src/cpu/x86/lapic/lapic.c
+++ b/src/cpu/x86/lapic/lapic.c
@@ -55,7 +55,7 @@ void setup_lapic(void)
 			LAPIC_DELIVERY_MODE_NMI)
 		);
 
-	printk_debug(" apic_id: %d ", lapicid());
+	printk_debug(" apic_id: 0x%02x ", lapicid());
 
 #else /* !NEED_LLAPIC */
 	/* Only Pentium Pro and later have those MSR stuff */
diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c
index 4b5acad2c4..1adafc8d18 100644
--- a/src/cpu/x86/lapic/lapic_cpu_init.c
+++ b/src/cpu/x86/lapic/lapic_cpu_init.c
@@ -322,7 +322,7 @@ static void start_other_cpus(struct bus *cpu_bus, device_t bsp_cpu)
 
 		if (!start_cpu(cpu)) {
 			/* Record the error in cpu? */
-			printk_err("CPU  %u would not start!\n",
+			printk_err("CPU 0x%02x would not start!\n",
 				cpu->path.u.apic.apic_id);
 		}
 #if SERIAL_CPU_INIT == 1
@@ -354,7 +354,7 @@ static void wait_other_cpus_stop(struct bus *cpu_bus)
 			continue;
 		}
 		if (!cpu->initialized) {
-			printk_err("CPU %u did not initialize!\n", 
+			printk_err("CPU 0x%02x did not initialize!\n", 
 				cpu->path.u.apic.apic_id);
 #warning "FIXME do I need a mainboard_cpu_fixup function?"
 		}
@@ -366,6 +366,10 @@ static void wait_other_cpus_stop(struct bus *cpu_bus)
 #define initialize_other_cpus(root) do {} while(0)
 #endif /* CONFIG_SMP */
 
+#if WAIT_BEFORE_CPUS_INIT==0
+	#define cpus_ready_for_init() do {} while(0)
+#endif
+
 void initialize_cpus(struct bus *cpu_bus)
 {
 	struct device_path cpu_path;
@@ -394,6 +398,8 @@ void initialize_cpus(struct bus *cpu_bus)
 	copy_secondary_start_to_1m_below(); // why here? In case some day we can start core1 in amd_sibling_init
 #endif
 	
+        cpus_ready_for_init(); 
+
 #if CONFIG_SMP == 1
 	#if SERIAL_CPU_INIT == 0
 	/* start all aps at first, so we can init ECC all together */
@@ -407,7 +413,6 @@ void initialize_cpus(struct bus *cpu_bus)
 
 #if CONFIG_SMP == 1
         #if SERIAL_CPU_INIT == 1
-        /* start all aps */
         start_other_cpus(cpu_bus, info->cpu);
         #endif
 
diff --git a/src/cpu/x86/mtrr/earlymtrr.c b/src/cpu/x86/mtrr/earlymtrr.c
index aea8e258d4..1c00bd7dcc 100644
--- a/src/cpu/x86/mtrr/earlymtrr.c
+++ b/src/cpu/x86/mtrr/earlymtrr.c
@@ -47,10 +47,29 @@ static void set_var_mtrr(
 	basem.hi = 0;
 	wrmsr(MTRRphysBase_MSR(reg), basem);
 	maskm.lo = ~(size - 1) | 0x800;
-	maskm.hi = 0x0f;
+	maskm.hi = (1<<(CPU_ADDR_BITS-32))-1;
 	wrmsr(MTRRphysMask_MSR(reg), maskm);
 }
 
+static void set_var_mtrr_x(
+        unsigned reg, uint32_t base_lo, uint32_t base_hi, uint32_t size_lo, uint32_t size_hi, unsigned type)
+
+{
+        /* Bit Bit 32-35 of MTRRphysMask should be set to 1 */
+        msr_t basem, maskm;
+        basem.lo = (base_lo & 0xfffff000) | type;
+        basem.hi = base_hi & ((1<<(CPU_ADDR_BITS-32))-1);
+        wrmsr(MTRRphysBase_MSR(reg), basem);
+       	maskm.hi = (1<<(CPU_ADDR_BITS-32))-1;
+	if(size_lo) {
+	        maskm.lo = ~(size_lo - 1) | 0x800;
+	} else {
+		maskm.lo = 0x800;
+		maskm.hi &= ~(size_hi - 1);
+	}
+        wrmsr(MTRRphysMask_MSR(reg), maskm);
+}
+
 static void cache_lbmem(int type)
 {
 	/* Enable caching for 0 - 1MB using variable mtrr */
@@ -70,7 +89,6 @@ static void do_early_mtrr_init(const unsigned long *mtrr_msrs)
 	 */
 	msr_t msr;
 	const unsigned long *msr_addr;
-	unsigned long cr0;
 
 	/* Inialize all of the relevant msrs to 0 */
 	msr.lo = 0;
diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c
index 1226713cf5..101d11d5e2 100644
--- a/src/cpu/x86/mtrr/mtrr.c
+++ b/src/cpu/x86/mtrr/mtrr.c
@@ -70,6 +70,25 @@ static void set_var_mtrr(
 	msr_t base, mask;
 	unsigned address_mask_high;
 
+        if (reg >= 8)
+                return;
+
+        // it is recommended that we disable and enable cache when we
+        // do this.
+        if (sizek == 0) {
+        	disable_cache();
+	
+                msr_t zero;
+                zero.lo = zero.hi = 0;
+                /* The invalid bit is kept in the mask, so we simply clear the
+                   relevant mask register to disable a range. */
+                wrmsr (MTRRphysMask_MSR(reg), zero);
+
+        	enable_cache();
+		return;
+        }
+
+
 	address_mask_high = ((1u << (address_bits - 32u)) - 1u);
 
 	base.hi = basek >> 22;
@@ -86,25 +105,16 @@ static void set_var_mtrr(
 		mask.lo = 0;
 	}
 
-	if (reg >= 8)
-		return;
-
 	// it is recommended that we disable and enable cache when we 
 	// do this. 
 	disable_cache();
-	if (sizek == 0) {
-		msr_t zero;
-		zero.lo = zero.hi = 0;
-		/* The invalid bit is kept in the mask, so we simply clear the
-		   relevant mask register to disable a range. */
-		wrmsr (MTRRphysMask_MSR(reg), zero);
-	} else {
-		/* Bit 32-35 of MTRRphysMask should be set to 1 */
-		base.lo |= type;
-		mask.lo |= 0x800;
-		wrmsr (MTRRphysBase_MSR(reg), base);
-		wrmsr (MTRRphysMask_MSR(reg), mask);
-	}
+
+	/* Bit 32-35 of MTRRphysMask should be set to 1 */
+	base.lo |= type;
+	mask.lo |= 0x800;
+	wrmsr (MTRRphysBase_MSR(reg), base);
+	wrmsr (MTRRphysMask_MSR(reg), mask);
+
 	enable_cache();
 }