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authorPatrick Georgi <patrick.georgi@secunet.com>2012-11-20 11:53:47 +0100
committerStefan Reinauer <stefan.reinauer@coreboot.org>2012-11-27 23:51:52 +0100
commite135ac5a7ea69b6edcb89345019212f5de412b1e (patch)
tree408611a9f2846867f9731af53b1f08dd32eb6851 /src/cpu/x86
parentbdc1816b2379bdf569ac6746172bba41e1307917 (diff)
downloadcoreboot-e135ac5a7ea69b6edcb89345019212f5de412b1e.tar.xz
Remove AMD special case for LAPIC based udelay()
- Optionally override FSB clock detection in generic LAPIC code with constant value. - Override on AMD Model fxx, 10xxx, agesa CPUs with 200MHz - compile LAPIC code for romstage, too - Remove #include ".../apic_timer.c" in AMD based mainboards - Remove custom udelay implementation from intel northbridges' romstages Future work: - remove the compile time special case (requires some cpuid based switching) - drop northbridge udelay implementations (i945, i5000) if not required anymore (eg. can SMM use the LAPIC timer?) Change-Id: I25bacaa2163f5e96ab7f3eaf1994ab6899eff054 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/1618 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/cpu/x86')
-rw-r--r--src/cpu/x86/Kconfig3
-rw-r--r--src/cpu/x86/lapic/Makefile.inc1
-rw-r--r--src/cpu/x86/lapic/apic_timer.c13
3 files changed, 16 insertions, 1 deletions
diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig
index 4300c3d0e4..ae3241e8b3 100644
--- a/src/cpu/x86/Kconfig
+++ b/src/cpu/x86/Kconfig
@@ -11,6 +11,9 @@ config UDELAY_LAPIC
bool
default n
+config UDELAY_LAPIC_FIXED_FSB
+ int
+
config UDELAY_TSC
bool
default n
diff --git a/src/cpu/x86/lapic/Makefile.inc b/src/cpu/x86/lapic/Makefile.inc
index f3fcadc0a7..6663c12880 100644
--- a/src/cpu/x86/lapic/Makefile.inc
+++ b/src/cpu/x86/lapic/Makefile.inc
@@ -1,5 +1,6 @@
ramstage-y += lapic.c
ramstage-y += lapic_cpu_init.c
ramstage-y += secondary.S
+romstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c
ramstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c
ramstage-y += boot_cpu.c
diff --git a/src/cpu/x86/lapic/apic_timer.c b/src/cpu/x86/lapic/apic_timer.c
index 562c79c2e8..53209fbbff 100644
--- a/src/cpu/x86/lapic/apic_timer.c
+++ b/src/cpu/x86/lapic/apic_timer.c
@@ -20,7 +20,9 @@
#include <stdint.h>
#include <delay.h>
+#include <arch/io.h>
#include <arch/cpu.h>
+#include <cpu/x86/car.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/lapic.h>
@@ -28,7 +30,15 @@
* memory init.
*/
-static u32 timer_fsb = 0;
+#if CONFIG_UDELAY_LAPIC_FIXED_FSB
+static const u32 timer_fsb = CONFIG_UDELAY_LAPIC_FIXED_FSB;
+
+static int set_timer_fsb(void)
+{
+ return 0;
+}
+#else
+static u32 timer_fsb CAR_GLOBAL = 0;
static int set_timer_fsb(void)
{
@@ -60,6 +70,7 @@ static int set_timer_fsb(void)
return 0;
}
+#endif
void init_timer(void)
{