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| author | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2011-04-14 22:28:00 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2011-04-14 22:28:00 +0000 |
| commit | 24ef134b37131064a6f45a221b6478e55f0a38ca (patch) | |
| tree | 8d6bfe6c51385a0eea20cbe5b5a9a1fbe50edd5e /src/cpu/x86 | |
| parent | 40e42a824b2800ed90614f3a5d3e5edf7cb877ff (diff) | |
| download | coreboot-24ef134b37131064a6f45a221b6478e55f0a38ca.tar.xz | |
drop half an uart8250 implementation from smiutil and use the common code
for that instead. This also allows using non-uart8250 consoles for smi
debugging.
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6501 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/x86')
| -rw-r--r-- | src/cpu/x86/smm/smiutil.c | 102 |
1 files changed, 22 insertions, 80 deletions
diff --git a/src/cpu/x86/smm/smiutil.c b/src/cpu/x86/smm/smiutil.c index 980ea69f51..cf951f4518 100644 --- a/src/cpu/x86/smm/smiutil.c +++ b/src/cpu/x86/smm/smiutil.c @@ -21,110 +21,52 @@ #include <arch/io.h> #include <arch/romcc_io.h> -#include <console/console.h> #include <cpu/x86/cache.h> #include <cpu/x86/smm.h> -/* ********************* smi_util ************************* */ - -/* Data */ -#define UART_RBR 0x00 -#define UART_TBR 0x00 - -/* Control */ -#define UART_IER 0x01 -#define UART_IIR 0x02 -#define UART_FCR 0x02 -#define UART_LCR 0x03 -#define UART_MCR 0x04 -#define UART_DLL 0x00 -#define UART_DLM 0x01 - -/* Status */ -#define UART_LSR 0x05 -#define UART_MSR 0x06 -#define UART_SCR 0x07 - -#ifndef CONFIG_TTYS0_BASE -#define CONFIG_TTYS0_BASE 0x3f8 -#endif - -#ifndef CONFIG_TTYS0_BAUD -#define CONFIG_TTYS0_BAUD 115200 +#include <console/console.h> +#include <console/vtxprintf.h> +#if CONFIG_CONSOLE_SERIAL8250 +#include <uart8250.h> #endif - -#ifndef CONFIG_TTYS0_DIV -#define CONFIG_TTYS0_DIV (115200/CONFIG_TTYS0_BAUD) +#if CONFIG_USBDEBUG +#include <usbdebug.h> #endif - -/* Line Control Settings */ -#ifndef CONFIG_TTYS0_LCS -/* Set 8bit, 1 stop bit, no parity */ -#define CONFIG_TTYS0_LCS 0x3 +#if CONFIG_CONSOLE_NE2K +#include <console/ne2k.h> #endif -#define UART_LCS CONFIG_TTYS0_LCS - -static int uart_can_tx_byte(void) -{ - return inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x20; -} - -static void uart_wait_to_tx_byte(void) -{ - while(!uart_can_tx_byte()) - ; -} - -static void uart_wait_until_sent(void) -{ - while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40)) - ; -} - -static void uart_tx_byte(unsigned char data) -{ - uart_wait_to_tx_byte(); - outb(data, CONFIG_TTYS0_BASE + UART_TBR); - /* Make certain the data clears the fifos */ - uart_wait_until_sent(); -} - void console_tx_flush(void) { - uart_wait_to_tx_byte(); + // the tx_byte functions take care of the flush. + // if not, this should be implemented. } void console_tx_byte(unsigned char byte) { if (byte == '\n') - uart_tx_byte('\r'); - uart_tx_byte(byte); -} + console_tx_byte('\r'); -#if CONFIG_DEBUG_SMI -static void uart_init(void) -{ - /* disable interrupts */ - outb(0x0, CONFIG_TTYS0_BASE + UART_IER); - /* enable fifo's */ - outb(0x01, CONFIG_TTYS0_BASE + UART_FCR); - /* Set Baud Rate Divisor to 12 ==> 115200 Baud */ - outb(0x80 | UART_LCS, CONFIG_TTYS0_BASE + UART_LCR); - outb(CONFIG_TTYS0_DIV & 0xFF, CONFIG_TTYS0_BASE + UART_DLL); - outb((CONFIG_TTYS0_DIV >> 8) & 0xFF, CONFIG_TTYS0_BASE + UART_DLM); - outb(UART_LCS, CONFIG_TTYS0_BASE + UART_LCR); -} +#if CONFIG_CONSOLE_SERIAL8250 + uart8250_tx_byte(CONFIG_TTYS0_BASE, byte); +#endif +#if CONFIG_USBDEBUG + usbdebug_tx_byte(byte); #endif +#if CONFIG_CONSOLE_NE2K + ne2k_append_data(&byte, 1, CONFIG_CONSOLE_NE2K_IO_PORT); +#endif +} void console_init(void) { #if CONFIG_DEBUG_SMI console_loglevel = CONFIG_DEFAULT_CONSOLE_LOGLEVEL; +#if CONFIG_CONSOLE_SERIAL8250 uart_init(); +#endif #else console_loglevel = 1; #endif } -/* ********************* smi_util ************************* */ |