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| author | Jacob Garber <jgarber1@ualberta.ca> | 2020-10-28 20:03:53 -0600 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2020-10-30 21:40:01 +0000 |
| commit | 1627e2f1586e44e8fafbc78c5a83f6fe90a10b1f (patch) | |
| tree | e5f7005a46f7de8f00786751602b6fe6514a2b40 /src/cpu/x86 | |
| parent | 1fa72d5fe1d2ac41036c08355c760fb576899347 (diff) | |
| download | coreboot-1627e2f1586e44e8fafbc78c5a83f6fe90a10b1f.tar.xz | |
cpu/x86/sipi_vector.S: Use correct suffix for bts
The assembler is warning that the bts instruction is ambiguous, so use
the correct suffix btsl. See also commit 693315160e
(cpu/x86/sipi_vector.S: Use correct op suffix)
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: I2eded0af1258e90926009544683b23961d99887b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46928
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/cpu/x86')
| -rw-r--r-- | src/cpu/x86/sipi_vector.S | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/x86/sipi_vector.S b/src/cpu/x86/sipi_vector.S index ba1ecb7de6..054f30d2c4 100644 --- a/src/cpu/x86/sipi_vector.S +++ b/src/cpu/x86/sipi_vector.S @@ -121,7 +121,7 @@ _start: /* Protect microcode loading. */ lock_microcode: - lock bts $0, microcode_lock + lock btsl $0, microcode_lock jc lock_microcode load_microcode: |