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| author | Arthur Heymans <arthur@aheymans.xyz> | 2018-04-10 13:34:24 +0200 |
|---|---|---|
| committer | Arthur Heymans <arthur@aheymans.xyz> | 2018-12-03 10:18:56 +0000 |
| commit | 4c65bfc3e88fe6f4d6441fb7e51f78ed22dea709 (patch) | |
| tree | 4e2a75d7f1c967e57bf20f7a2854695c69d37cec /src/cpu/x86 | |
| parent | cf3076eff17dc9c152fca6ec9012e7734ff88b4c (diff) | |
| download | coreboot-4c65bfc3e88fe6f4d6441fb7e51f78ed22dea709.tar.xz | |
nb/intel/x4x: Use common code for SMM in TSEG
This also caches the TSEG region and therefore increases MTRR usage
a little in some cases.
Currently SMRR msr's are not set on model_1067x and model_6fx since
this needs the MSRR enable bit and lock set in IA32_FEATURE_CONTROL.
This will be handled properly in the subsequent parallel mp init
patchset.
Tested on Intel DG41WV, resume from S3 still works fine.
Change-Id: I317c5ca34bd38c3d42bf0d4e929b2a225a8a82dc
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/25597
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu/x86')
| -rw-r--r-- | src/cpu/x86/smm/smmrelocate.S | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/src/cpu/x86/smm/smmrelocate.S b/src/cpu/x86/smm/smmrelocate.S index 16bccbce45..bd12581a76 100644 --- a/src/cpu/x86/smm/smmrelocate.S +++ b/src/cpu/x86/smm/smmrelocate.S @@ -27,9 +27,6 @@ #include <southbridge/intel/i82801dx/i82801dx.h> #elif IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801IX) #include <southbridge/intel/i82801ix/i82801ix.h> -#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801JX) -#include <southbridge/intel/i82801jx/i82801jx.h> - #else #error "Southbridge needs SMM handler support." #endif |