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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2020-06-13 20:34:54 +0300 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2020-06-15 19:14:13 +0000 |
| commit | 61ba7fb2d9ecd2cfd64dda0618d544e4429fee8e (patch) | |
| tree | de32fc507063e0aa1e4a8fbdc4519f5e733f652c /src/cpu/x86 | |
| parent | 44ef38f70344f44ee53a3883515246172eb75054 (diff) | |
| download | coreboot-61ba7fb2d9ecd2cfd64dda0618d544e4429fee8e.tar.xz | |
cpu/intel: Remove obsolete comment in CAR setup
A looong time ago when cache_as_ram.S was built into romstage,
the stage was also linked twice. First at a fixed low address
and then again relocated at the final execute-in-place address.
Change-Id: Ic624feef6794f2c24e38459a45583d84fc07a484
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42347
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/cpu/x86')
0 files changed, 0 insertions, 0 deletions