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authorKyösti Mälkki <kyosti.malkki@gmail.com>2020-11-19 16:41:28 +0200
committerHung-Te Lin <hungte@chromium.org>2020-12-16 06:31:55 +0000
commit97b76f71915663aae82ca81568363eeda17fff87 (patch)
tree4403211b76e33c7e699d5802214b5d56acdc6f2e /src/cpu/x86
parent54b5e20cf87855324403689f0f05fba16267b7c4 (diff)
downloadcoreboot-97b76f71915663aae82ca81568363eeda17fff87.tar.xz
arch/x86: Link gdt_init.S into bootblock
Followup work forces gdtptr and gdt towards the top of bootblock. They need to be realmode-addressable, i.e. within top 64 KiB or same segment with .reset. Change-Id: Ib6f23b2808d0a7e0d277d00a9b0f30c49fdefdd5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47965 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/cpu/x86')
-rw-r--r--src/cpu/x86/16bit/entry16.inc2
-rw-r--r--src/cpu/x86/32bit/entry32.inc1
2 files changed, 1 insertions, 2 deletions
diff --git a/src/cpu/x86/16bit/entry16.inc b/src/cpu/x86/16bit/entry16.inc
index 2665cc69ae..5e90da1413 100644
--- a/src/cpu/x86/16bit/entry16.inc
+++ b/src/cpu/x86/16bit/entry16.inc
@@ -124,7 +124,7 @@ _start16bit:
ljmpl $ROM_CODE_SEG, $__protected_start
/**
- * The gdt is defined in entry32.inc, it has a 4 Gb code segment
+ * The gdt is defined in gdt_init.S, it has a 4 Gb code segment
* at 0x08, and a 4 GB data segment at 0x10;
*/
__gdtptr:
diff --git a/src/cpu/x86/32bit/entry32.inc b/src/cpu/x86/32bit/entry32.inc
index 85094483e5..873a809616 100644
--- a/src/cpu/x86/32bit/entry32.inc
+++ b/src/cpu/x86/32bit/entry32.inc
@@ -4,7 +4,6 @@
#include <arch/rom_segs.h>
#include <cpu/x86/post_code.h>
-#include <arch/x86/gdt_init.S>
.code32
/*