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authorAngel Pons <th3fanbus@gmail.com>2019-11-02 18:39:44 +0100
committerNico Huber <nico.h@gmx.de>2019-11-03 20:48:18 +0000
commitbda870242e16d3406eb1598059b587aee2856dd6 (patch)
tree0f0b07412d30fb4e6cc7a6a6fb109f67cbdda0b3 /src/cpu/x86
parent5ff6a6af0e93a8ad9383bc4c7db079b40133b0d2 (diff)
downloadcoreboot-bda870242e16d3406eb1598059b587aee2856dd6.tar.xz
cpu/x86/mtrr/xip_cache.c: Fix inconsistent message
Change-Id: Ic99e61632664f86cc12507f2ddffa364fdd79202 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36585 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu/x86')
-rw-r--r--src/cpu/x86/mtrr/xip_cache.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/x86/mtrr/xip_cache.c b/src/cpu/x86/mtrr/xip_cache.c
index 112c0dfb90..9968eea78e 100644
--- a/src/cpu/x86/mtrr/xip_cache.c
+++ b/src/cpu/x86/mtrr/xip_cache.c
@@ -63,7 +63,7 @@ void platform_prog_run(struct prog *prog)
if (cpu_info.x86 == 0xf) {
printk(BIOS_NOTICE,
"PROG_RUN: CPU does not support caching ROM\n"
- "The next stage will run slowly\n");
+ "The next stage will run slowly!\n");
return;
}