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authorPatrick Rudolph <siro@das-labor.org>2019-11-12 16:30:14 +0100
committerPatrick Georgi <pgeorgi@google.com>2020-06-22 11:52:49 +0000
commitfc57d6c4c2848726be1361f6dee3c33e7551b857 (patch)
tree123d06ba53ecde7fcb836938cecb9eb0a199c922 /src/cpu/x86
parent6f1d35e72dcc0d2ded8c5ebe15d8d9cf9c9ba5cb (diff)
downloadcoreboot-fc57d6c4c2848726be1361f6dee3c33e7551b857.tar.xz
cpu/x86/lapic: Support x86_64 and clean up code
Most LAPIC registers are 32bit, and thus the use of long is valid on x86_32, however it doesn't work on x86_64. * Don't use long as it is 64bit on x86_64, which breaks interrupts in QEMU and thus SeaBIOS wouldn't time out the boot menu * Get rid of unused defines * Get rid of unused atomic xchg code Tested on QEMU Q35 with x86_64 enabled: Interrupts work again. Tested on QEMU Q35 with x86_32 enabled: Interrupts are still working. Tested on Lenovo T410 with x86_64 enabled. Change-Id: Iaed1ad956d090625c7bb5cd9cf55cbae16dd82bd Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36777 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu/x86')
-rw-r--r--src/cpu/x86/lapic/lapic.c2
-rw-r--r--src/cpu/x86/lapic/lapic_cpu_init.c8
2 files changed, 5 insertions, 5 deletions
diff --git a/src/cpu/x86/lapic/lapic.c b/src/cpu/x86/lapic/lapic.c
index f0a6cd7f46..04ce2261de 100644
--- a/src/cpu/x86/lapic/lapic.c
+++ b/src/cpu/x86/lapic/lapic.c
@@ -47,6 +47,6 @@ void do_lapic_init(void)
LAPIC_DELIVERY_MODE_NMI)
);
- printk(BIOS_DEBUG, " apic_id: 0x%02lx ", lapicid());
+ printk(BIOS_DEBUG, " apic_id: 0x%02x ", lapicid());
printk(BIOS_INFO, "done.\n");
}
diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c
index 58a633b34c..f89d9e3928 100644
--- a/src/cpu/x86/lapic/lapic_cpu_init.c
+++ b/src/cpu/x86/lapic/lapic_cpu_init.c
@@ -91,7 +91,7 @@ static void recover_lowest_1M(void)
static int lapic_start_cpu(unsigned long apicid)
{
int timeout;
- unsigned long send_status, accept_status;
+ uint32_t send_status, accept_status;
int j, maxlvt;
/*
@@ -123,11 +123,11 @@ static int lapic_start_cpu(unsigned long apicid)
printk(BIOS_ERR, "CPU %ld: First APIC write timed out. "
"Disabling\n", apicid);
// too bad.
- printk(BIOS_ERR, "ESR is 0x%lx\n", lapic_read(LAPIC_ESR));
+ printk(BIOS_ERR, "ESR is 0x%x\n", lapic_read(LAPIC_ESR));
if (lapic_read(LAPIC_ESR)) {
printk(BIOS_ERR, "Try to reset ESR\n");
lapic_write_around(LAPIC_ESR, 0);
- printk(BIOS_ERR, "ESR is 0x%lx\n",
+ printk(BIOS_ERR, "ESR is 0x%x\n",
lapic_read(LAPIC_ESR));
}
return 0;
@@ -216,7 +216,7 @@ static int lapic_start_cpu(unsigned long apicid)
if (send_status)
printk(BIOS_WARNING, "APIC never delivered???\n");
if (accept_status)
- printk(BIOS_WARNING, "APIC delivery error (%lx).\n",
+ printk(BIOS_WARNING, "APIC delivery error (%x).\n",
accept_status);
if (send_status || accept_status)
return 0;