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| author | Stefan Reinauer <reinauer@chromium.org> | 2012-08-07 14:44:51 -0700 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2012-08-09 00:38:39 +0200 |
| commit | 0db6820b10c3452764ab62173c3b75cefbf6c215 (patch) | |
| tree | 95abc6378ed60c37e14de842a7baf014dc60111b /src/cpu/x86 | |
| parent | 4c29d7f27d315ab93c811fb86ba246151dc84da3 (diff) | |
| download | coreboot-0db6820b10c3452764ab62173c3b75cefbf6c215.tar.xz | |
Synchronize rdtsc instructions
The CPU can arbitrarily reorder calls to rdtsc, significantly
reducing the precision of timing using the CPUs time stamp counter.
Unfortunately the method of synchronizing rdtsc is different
on AMD and Intel CPUs. There is a generic method, using the cpuid
instruction, but that uses up a lot of registers, and is very slow.
Hence, use the correct lfence/mfence instructions (for CPUs that
we know support it)
Change-Id: I17ecb48d283f38f23148c13159aceda704c64ea5
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1422
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/cpu/x86')
| -rw-r--r-- | src/cpu/x86/Kconfig | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 07e9d9ecbf..9a96aeadd8 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -23,6 +23,22 @@ config TSC_CALIBRATE_WITH_IO bool default n +config TSC_SYNC_LFENCE + bool + default n + help + The CPU driver should select this if the CPU needs + to execute an lfence instruction in order to synchronize + rdtsc. This is true for all modern AMD CPUs. + +config TSC_SYNC_MFENCE + bool + default n + help + The CPU driver should select this if the CPU needs + to execute an mfence instruction in order to synchronize + rdtsc. This is true for all modern Intel CPUs. + config XIP_ROM_SIZE hex default ROM_SIZE if ROMCC |