summaryrefslogtreecommitdiff
path: root/src/cpu
diff options
context:
space:
mode:
authorStefan Reinauer <stepan@coresystems.de>2010-04-01 09:50:32 +0000
committerStefan Reinauer <stepan@openbios.org>2010-04-01 09:50:32 +0000
commit0c781b2694b2c137d9761704954ea38be5ba8a15 (patch)
tree55c8bb4ea9f5875da7e4f7ffa6b5e7d2aa87a4b8 /src/cpu
parent84b685af5f1e1cf49c2c2f22ae80a8a0df8472f8 (diff)
downloadcoreboot-0c781b2694b2c137d9761704954ea38be5ba8a15.tar.xz
- get rid of ASM_CONSOLE_LOGLEVEL except in two assembler files.
- start naming all versions of post code output "post_code()" Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5344 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/amd/model_lx/cache_as_ram.inc8
-rw-r--r--src/cpu/intel/model_106cx/cache_as_ram.inc1
-rw-r--r--src/cpu/intel/model_6ex/cache_as_ram.inc1
-rw-r--r--src/cpu/intel/model_6fx/cache_as_ram.inc1
-rw-r--r--src/cpu/x86/32bit/entry32.inc2
5 files changed, 7 insertions, 6 deletions
diff --git a/src/cpu/amd/model_lx/cache_as_ram.inc b/src/cpu/amd/model_lx/cache_as_ram.inc
index 659e0141a8..7e6a68a5ad 100644
--- a/src/cpu/amd/model_lx/cache_as_ram.inc
+++ b/src/cpu/amd/model_lx/cache_as_ram.inc
@@ -17,6 +17,10 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
+#ifndef ASM_CONSOLE_LOGLEVEL
+#define ASM_CONSOLE_LOGLEVEL CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
+#endif
+
#define LX_STACK_BASE CONFIG_DCACHE_RAM_BASE /* this is where the DCache will be mapped and be used as stack, It would be cool if it was the same base as coreboot normal stack */
#define LX_STACK_END LX_STACK_BASE+(CONFIG_DCACHE_RAM_SIZE-1)
@@ -206,7 +210,7 @@ __main:
* isn\'t really that big we just copy/clear using bytes, not
* double words.
*/
- intel_chip_post_macro(0x11) /* post 11 */
+ post_code(0x11) /* post 11 */
cld /* clear direction flag */
@@ -220,7 +224,7 @@ __main:
call cbfs_and_run_core
.Lhlt:
- intel_chip_post_macro(0xee) /* post fail ee */
+ post_code(0xee) /* post fail ee */
hlt
jmp .Lhlt
diff --git a/src/cpu/intel/model_106cx/cache_as_ram.inc b/src/cpu/intel/model_106cx/cache_as_ram.inc
index 4781b0521c..da42d4dc66 100644
--- a/src/cpu/intel/model_106cx/cache_as_ram.inc
+++ b/src/cpu/intel/model_106cx/cache_as_ram.inc
@@ -20,7 +20,6 @@
#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
-#define post_code(x) intel_chip_post_macro(x)
#include <cpu/x86/mtrr.h>
#include <cpu/amd/mtrr.h>
diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc
index 848c84d2c2..ad0567e102 100644
--- a/src/cpu/intel/model_6ex/cache_as_ram.inc
+++ b/src/cpu/intel/model_6ex/cache_as_ram.inc
@@ -20,7 +20,6 @@
#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
-#define post_code(x) intel_chip_post_macro(x)
#include <cpu/x86/mtrr.h>
#include <cpu/amd/mtrr.h>
diff --git a/src/cpu/intel/model_6fx/cache_as_ram.inc b/src/cpu/intel/model_6fx/cache_as_ram.inc
index 50f9608dcc..b902b1dbf6 100644
--- a/src/cpu/intel/model_6fx/cache_as_ram.inc
+++ b/src/cpu/intel/model_6fx/cache_as_ram.inc
@@ -20,7 +20,6 @@
#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
-#define post_code(x) intel_chip_post_macro(x)
#include <cpu/x86/mtrr.h>
#include <cpu/amd/mtrr.h>
diff --git a/src/cpu/x86/32bit/entry32.inc b/src/cpu/x86/32bit/entry32.inc
index 2cea40f8a7..bc5e4436ae 100644
--- a/src/cpu/x86/32bit/entry32.inc
+++ b/src/cpu/x86/32bit/entry32.inc
@@ -50,7 +50,7 @@ __protected_start:
/* Save the BIST value */
movl %eax, %ebp
- intel_chip_post_macro(0x10) /* post 10 */
+ post_code(0x10) /* post 10 */
movw $ROM_DATA_SEG, %ax
movw %ax, %ds