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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2014-10-16 12:47:25 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2014-10-19 06:14:05 +0200 |
| commit | 1729cd85744129104e3e41aac1f18e43b62f79ff (patch) | |
| tree | 37a9e44516fc1d1da23e75266aa672099a2872f2 /src/cpu | |
| parent | d05d0db0d0cb76776addbd75d264e713dda47880 (diff) | |
| download | coreboot-1729cd85744129104e3e41aac1f18e43b62f79ff.tar.xz | |
x86 romstage: Move stack just below RAMTOP
Placement of romstage stack in RAM was vulnerable for getting corrupted
by decompressed ramstage.
Change-Id: Ic032bd3e69f4ab8dab8e5932df39fab70aa3e769
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7096
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/intel/car/cache_as_ram.inc | 3 | ||||
| -rw-r--r-- | src/cpu/intel/car/cache_as_ram_ht.inc | 3 | ||||
| -rw-r--r-- | src/cpu/intel/haswell/cache_as_ram.inc | 1 | ||||
| -rw-r--r-- | src/cpu/intel/haswell/romstage.c | 3 | ||||
| -rw-r--r-- | src/cpu/intel/model_2065x/cache_as_ram.inc | 3 | ||||
| -rw-r--r-- | src/cpu/intel/model_206ax/cache_as_ram.inc | 3 | ||||
| -rw-r--r-- | src/cpu/intel/model_6ex/cache_as_ram.inc | 3 | ||||
| -rw-r--r-- | src/cpu/via/car/cache_as_ram.inc | 3 |
8 files changed, 7 insertions, 15 deletions
diff --git a/src/cpu/intel/car/cache_as_ram.inc b/src/cpu/intel/car/cache_as_ram.inc index 1ea50b8b37..843ca2dfd8 100644 --- a/src/cpu/intel/car/cache_as_ram.inc +++ b/src/cpu/intel/car/cache_as_ram.inc @@ -21,7 +21,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <cpu/x86/stack.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/cache.h> #include <cpu/x86/lapic_def.h> @@ -361,7 +360,7 @@ __main: post_code(POST_PREPARE_RAMSTAGE) cld /* Clear direction flag. */ - movl $ROMSTAGE_STACK, %esp + movl $CONFIG_RAMTOP, %esp movl %esp, %ebp call copy_and_run diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc index fb653168b2..265cd4f247 100644 --- a/src/cpu/intel/car/cache_as_ram_ht.inc +++ b/src/cpu/intel/car/cache_as_ram_ht.inc @@ -20,7 +20,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <cpu/x86/stack.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/cache.h> #include <cpu/x86/post_code.h> @@ -430,7 +429,7 @@ __main: post_code(POST_PREPARE_RAMSTAGE) cld /* Clear direction flag. */ - movl $ROMSTAGE_STACK, %esp + movl $CONFIG_RAMTOP, %esp movl %esp, %ebp call copy_and_run diff --git a/src/cpu/intel/haswell/cache_as_ram.inc b/src/cpu/intel/haswell/cache_as_ram.inc index 36d56545da..51ac536f72 100644 --- a/src/cpu/intel/haswell/cache_as_ram.inc +++ b/src/cpu/intel/haswell/cache_as_ram.inc @@ -18,7 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <cpu/x86/stack.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/cache.h> #include <cpu/x86/post_code.h> diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 9e2766808d..65ee3b47e0 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -25,7 +25,6 @@ #include <cpu/x86/bist.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> -#include <cpu/x86/stack.h> #include <lib.h> #include <timestamp.h> #include <arch/io.h> @@ -85,7 +84,7 @@ static unsigned long choose_top_of_stack(void) ROMSTAGE_RAM_STACK_SIZE); stack_top += ROMSTAGE_RAM_STACK_SIZE; #else - stack_top = ROMSTAGE_STACK; + stack_top = CONFIG_RAMTOP; #endif return stack_top; } diff --git a/src/cpu/intel/model_2065x/cache_as_ram.inc b/src/cpu/intel/model_2065x/cache_as_ram.inc index 21f626b9de..43d51dae1a 100644 --- a/src/cpu/intel/model_2065x/cache_as_ram.inc +++ b/src/cpu/intel/model_2065x/cache_as_ram.inc @@ -18,7 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <cpu/x86/stack.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/cache.h> #include <cpu/x86/post_code.h> @@ -278,7 +277,7 @@ __main: post_code(POST_PREPARE_RAMSTAGE) cld /* Clear direction flag. */ - movl $ROMSTAGE_STACK, %esp + movl $CONFIG_RAMTOP, %esp movl %esp, %ebp call copy_and_run diff --git a/src/cpu/intel/model_206ax/cache_as_ram.inc b/src/cpu/intel/model_206ax/cache_as_ram.inc index 1a197071c4..bf377f5b95 100644 --- a/src/cpu/intel/model_206ax/cache_as_ram.inc +++ b/src/cpu/intel/model_206ax/cache_as_ram.inc @@ -18,7 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <cpu/x86/stack.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/cache.h> #include <cpu/x86/post_code.h> @@ -311,7 +310,7 @@ __main: post_code(POST_PREPARE_RAMSTAGE) cld /* Clear direction flag. */ - movl $ROMSTAGE_STACK, %esp + movl $CONFIG_RAMTOP, %esp movl %esp, %ebp call copy_and_run diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc index baf4ae8617..09b8e93ce5 100644 --- a/src/cpu/intel/model_6ex/cache_as_ram.inc +++ b/src/cpu/intel/model_6ex/cache_as_ram.inc @@ -18,7 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <cpu/x86/stack.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/cache.h> #include <cpu/x86/post_code.h> @@ -224,7 +223,7 @@ __main: post_code(POST_PREPARE_RAMSTAGE) cld /* Clear direction flag. */ - movl $ROMSTAGE_STACK, %esp + movl $CONFIG_RAMTOP, %esp movl %esp, %ebp call copy_and_run diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc index 17b4b833db..c8a7e4038c 100644 --- a/src/cpu/via/car/cache_as_ram.inc +++ b/src/cpu/via/car/cache_as_ram.inc @@ -25,7 +25,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <cpu/x86/stack.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/cache.h> #include <console/post_codes.h> @@ -268,7 +267,7 @@ __main: post_code(POST_PREPARE_RAMSTAGE) cld /* Clear direction flag. */ - movl $ROMSTAGE_STACK, %esp + movl $CONFIG_RAMTOP, %esp movl %esp, %ebp call copy_and_run |