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authorAndreas Schultz <aschultz@tpip.net>2010-08-30 16:16:01 +0000
committerStefan Reinauer <stepan@openbios.org>2010-08-30 16:16:01 +0000
commit1bab1fb839c59594b8dd0e48d35c15353266d6ad (patch)
tree7a1e5c11b37f44fe7849f1081e2f202cdf0d7c30 /src/cpu
parent819ee74888c7c482cfec037b28dc37bbc2fb1ef1 (diff)
downloadcoreboot-1bab1fb839c59594b8dd0e48d35c15353266d6ad.tar.xz
mPGA479M Sockets can take Intel Mobile Celeron.
The 1.2GHz model has CPUID F29. This adds them to the list of CPUs for that socket. Signed-off-by: Andreas Schultz <aschultz@tpip.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> This patch likely breaks the following two boards since it unconditionally activates CAR code for this socket: * digitallogic/adl855pc * intel/mtarvon stepan suggests moving those two boards over to CAR, too, so we don't have to worry. --- src/cpu/intel/socket_mPGA479M/Kconfig | 1 + src/cpu/intel/socket_mPGA479M/Makefile.inc | 2 ++ 2 files changed, 3 insertions(+), 0 deletions(-) git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5750 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/intel/socket_mPGA479M/Kconfig1
-rw-r--r--src/cpu/intel/socket_mPGA479M/Makefile.inc2
2 files changed, 3 insertions, 0 deletions
diff --git a/src/cpu/intel/socket_mPGA479M/Kconfig b/src/cpu/intel/socket_mPGA479M/Kconfig
index 4ee8e1b215..8598eaf5aa 100644
--- a/src/cpu/intel/socket_mPGA479M/Kconfig
+++ b/src/cpu/intel/socket_mPGA479M/Kconfig
@@ -3,5 +3,6 @@ config CPU_INTEL_SOCKET_MPGA479M
select CPU_INTEL_MODEL_69X
select CPU_INTEL_MODEL_6BX
select CPU_INTEL_MODEL_6DX
+ select CPU_INTEL_MODEL_F2X
select MMX
select SSE
diff --git a/src/cpu/intel/socket_mPGA479M/Makefile.inc b/src/cpu/intel/socket_mPGA479M/Makefile.inc
index d16cc76407..2cf418fd11 100644
--- a/src/cpu/intel/socket_mPGA479M/Makefile.inc
+++ b/src/cpu/intel/socket_mPGA479M/Makefile.inc
@@ -1,6 +1,7 @@
obj-y += socket_mPGA479M.o
subdirs-y += ../model_69x
subdirs-y += ../model_6dx
+subdirs-y += ../model_f2x
subdirs-y += ../../x86/tsc
subdirs-y += ../../x86/mtrr
subdirs-y += ../../x86/lapic
@@ -9,3 +10,4 @@ subdirs-y += ../../x86/smm
subdirs-y += ../microcode
subdirs-y += ../hyperthreading
+cpu_incs += $(src)/cpu/intel/car/cache_as_ram.inc \ No newline at end of file