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| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2019-07-09 13:39:44 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2019-07-11 15:01:24 +0000 |
| commit | 20cfc87ca07ce1ac07c47480e1a6a5bc0a1e1090 (patch) | |
| tree | 35ef6620911b058fa57a5313d43b1842c00b5217 /src/cpu | |
| parent | 565b0aada93a0ef40b022b9b78b1bcefdf5193bb (diff) | |
| download | coreboot-20cfc87ca07ce1ac07c47480e1a6a5bc0a1e1090.tar.xz | |
soc/intel/cannonlake: Make EC S0ix notification optional in LPIT
Only call the \_SB.PCI0.LPCB.EC0.S0IX method if it exists.
Change-Id: Idf465f8ad7cb016f3ad3d9710b46e35f66f8939b
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Diffstat (limited to 'src/cpu')
0 files changed, 0 insertions, 0 deletions