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authorMyles Watson <mylesgw@gmail.com>2009-07-02 18:56:24 +0000
committerMyles Watson <mylesgw@gmail.com>2009-07-02 18:56:24 +0000
commit29cc9eda2021a87396ef31a6fc81daff6fd1be7a (patch)
treed3dfa07ca85547c77c5d07825fc8afcc19489076 /src/cpu
parent2468331952bae0abdc4d76dbe6cf26f05b7825e5 (diff)
downloadcoreboot-29cc9eda2021a87396ef31a6fc81daff6fd1be7a.tar.xz
Move the v3 resource allocator to v2.
Major changes: 1. Separate resource allocation into: A. Read Resources B. Avoid fixed resources (constrain limits) C. Allocate resources D. Set resources Usage notes: Resources which have IORESOURCE_FIXED set in the flags constrain the placement of other resources. All fixed resources will end up outside (above or below) the allocated resources. Domains usually start with base = 0 and limit = 2^address_bits - 1. I've added an IOAPIC to all platforms so that the old limit of 0xfec00000 is still there for resources. Some platforms may want to change that, but I didn't want to break anyone's board. Resources are allocated in a single block for memory and another for I/O. Currently the resource allocator doesn't support holes. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4394 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/amd/sc520/sc520.c49
-rw-r--r--src/cpu/emulation/qemu-x86/northbridge.c48
-rw-r--r--src/cpu/ppc/ppc4xx/pci_domain.c21
3 files changed, 45 insertions, 73 deletions
diff --git a/src/cpu/amd/sc520/sc520.c b/src/cpu/amd/sc520/sc520.c
index 90f1e0b049..8b21545d48 100644
--- a/src/cpu/amd/sc520/sc520.c
+++ b/src/cpu/amd/sc520/sc520.c
@@ -62,9 +62,27 @@ void sc520_enable_resources(struct device *dev) {
}
+static void sc520_read_resources(device_t dev)
+{
+ struct resource* res;
+
+ pci_dev_read_resources(dev);
+
+ res = new_resource(dev, 1);
+ res->base = 0x0UL;
+ res->size = 0x400UL;
+ res->limit = 0xffffUL;
+ res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+ res = new_resource(dev, 3); /* IOAPIC */
+ res->base = 0xfec00000;
+ res->size = 0x00001000;
+ res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+}
+
static struct device_operations cpu_operations = {
- .read_resources = pci_dev_read_resources,
+ .read_resources = sc520_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = sc520_enable_resources,
.init = cpu_init,
@@ -78,25 +96,6 @@ static const struct pci_driver cpu_driver __pci_driver = {
.device = 0x3000
};
-
-
-#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
-
-static void pci_domain_read_resources(device_t dev)
-{
- struct resource *resource;
- printk_spew("%s\n", __func__);
- /* Initialize the system wide io space constraints */
- resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
- resource->limit = 0xffffUL;
- resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-
- /* Initialize the system wide memory resources constraints */
- resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));
- resource->limit = 0xffffffffULL;
- resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-}
-
static void ram_resource(device_t dev, unsigned long index,
unsigned long basek, unsigned long sizek)
{
@@ -184,14 +183,6 @@ static void pci_domain_set_resources(device_t dev)
assign_resources(&dev->link[0]);
}
-static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
-{
- printk_spew("%s\n", __func__);
- max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
- return max;
-}
-
-
#if 0
void sc520_enable_resources(device_t dev) {
@@ -219,7 +210,7 @@ static struct device_operations pci_domain_ops = {
* If enable_resources is set to the generic enable_resources
* function the whole thing will hang in an endless loop on
* the ts5300. If this is really needed on another platform,
- * something is conceptionally wrong.
+ * something is conceptually wrong.
*/
.enable_resources = 0, //enable_resources,
.init = 0,
diff --git a/src/cpu/emulation/qemu-x86/northbridge.c b/src/cpu/emulation/qemu-x86/northbridge.c
index 993bffb4b8..b45315e899 100644
--- a/src/cpu/emulation/qemu-x86/northbridge.c
+++ b/src/cpu/emulation/qemu-x86/northbridge.c
@@ -9,23 +9,6 @@
#include "chip.h"
#include "northbridge.h"
-#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
-
-static void pci_domain_read_resources(device_t dev)
-{
- struct resource *resource;
-
- /* Initialize the system wide io space constraints */
- resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
- resource->limit = 0xffffUL;
- resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-
- /* Initialize the system wide memory resources constraints */
- resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));
- resource->limit = 0xffffffffULL;
- resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-}
-
static void ram_resource(device_t dev, unsigned long index,
unsigned long basek, unsigned long sizek)
{
@@ -70,7 +53,7 @@ static uint32_t find_pci_tolm(struct bus *bus)
extern uint64_t high_tables_base, high_tables_size;
#endif
-static void pci_domain_set_resources(device_t dev)
+static void cpu_pci_domain_set_resources(device_t dev)
{
static const uint8_t ramregs[] = {
0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, 0x56, 0x57
@@ -127,15 +110,34 @@ static void pci_domain_set_resources(device_t dev)
assign_resources(&dev->link[0]);
}
-static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
+static void cpu_pci_domain_read_resources(struct device *dev)
{
- max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
- return max;
+ struct resource *res;
+
+ pci_domain_read_resources(dev);
+
+ /* Reserve space for the IOAPIC. This should be in the Southbridge,
+ * but I couldn't tell which device to put it in. */
+ res = new_resource(dev, 2);
+ res->base = 0xfec00000UL;
+ res->size = 0x100000UL;
+ res->limit = 0xffffffffUL;
+ res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED |
+ IORESOURCE_ASSIGNED;
+
+ /* Reserve space for the LAPIC. There's one in every processor, but
+ * the space only needs to be reserved once, so we do it here. */
+ res = new_resource(dev, 3);
+ res->base = 0xfee00000UL;
+ res->size = 0x10000UL;
+ res->limit = 0xffffffffUL;
+ res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED |
+ IORESOURCE_ASSIGNED;
}
static struct device_operations pci_domain_ops = {
- .read_resources = pci_domain_read_resources,
- .set_resources = pci_domain_set_resources,
+ .read_resources = cpu_pci_domain_read_resources,
+ .set_resources = cpu_pci_domain_set_resources,
.enable_resources = enable_childrens_resources,
.init = 0,
.scan_bus = pci_domain_scan_bus,
diff --git a/src/cpu/ppc/ppc4xx/pci_domain.c b/src/cpu/ppc/ppc4xx/pci_domain.c
index b0da1f0263..6b8b74f461 100644
--- a/src/cpu/ppc/ppc4xx/pci_domain.c
+++ b/src/cpu/ppc/ppc4xx/pci_domain.c
@@ -7,27 +7,6 @@
#include <device/pci_ids.h>
#include <console/console.h>
-static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
-{
- max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
- return max;
-}
-
-static void pci_domain_read_resources(device_t dev)
-{
- struct resource *resource;
-
- /* Initialize the system wide io space constraints */
- resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
- resource->limit = 0xffffUL;
- resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-
- /* Initialize the system wide memory resources constraints */
- resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));
- resource->limit = 0xffffffffULL;
- resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-}
-
static void ram_resource(device_t dev, unsigned long index,
unsigned long basek, unsigned long sizek)
{