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authorArthur Heymans <arthur@aheymans.xyz>2017-04-28 22:36:17 +0200
committerStefan Reinauer <stefan.reinauer@coreboot.org>2017-06-28 00:48:41 +0000
commit3b633bbf1dfcd9107b8a1cc86ce8c34f6fc06fdb (patch)
tree70219f30ba14855f4e97e570dc3aeb3675c5cf38 /src/cpu
parent27e1801ea79b591f8a34591bc1a3576dd66406ba (diff)
downloadcoreboot-3b633bbf1dfcd9107b8a1cc86ce8c34f6fc06fdb.tar.xz
cpu/intel/pineview: Include speedstep
Needed to generate cpu entries. Change-Id: Ia3f5137c7642bb9f79562cc9d6e6881aca749179 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19496 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/intel/socket_FCBGA559/Makefile.inc1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/cpu/intel/socket_FCBGA559/Makefile.inc b/src/cpu/intel/socket_FCBGA559/Makefile.inc
index 082c47261b..dbf300b0d2 100644
--- a/src/cpu/intel/socket_FCBGA559/Makefile.inc
+++ b/src/cpu/intel/socket_FCBGA559/Makefile.inc
@@ -6,6 +6,7 @@ subdirs-y += ../../x86/cache
subdirs-y += ../../x86/smm
subdirs-y += ../microcode
subdirs-y += ../hyperthreading
+subdirs-y += ../speedstep
cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc
romstage-y += ../car/romstage.c