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authorAngel Pons <th3fanbus@gmail.com>2020-10-28 22:35:16 +0100
committerNico Huber <nico.h@gmx.de>2021-01-11 23:41:28 +0000
commit4f31cdfa2c90e2233e5cdae15961555d9f4abbec (patch)
treea7327768969bb8a032f2ff4f124fa3673c7ef319 /src/cpu
parent712ca3193307d170ed00a617a05d4cd3c539a02a (diff)
downloadcoreboot-4f31cdfa2c90e2233e5cdae15961555d9f4abbec.tar.xz
cpu/intel/haswell: Do not set PMG_IO_CAPTURE_BASE MSR
The MSR only needs to be set when IO MWAIT redirection is to be enabled. This was copied from Sandy Bridge, which already had this inconsistency. Change-Id: I424333afd654db9a7e180e9a2c31d369e3d92fd6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46917 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/intel/haswell/haswell_init.c6
1 files changed, 0 insertions, 6 deletions
diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c
index 44bbbfdadf..ff9573f6f8 100644
--- a/src/cpu/intel/haswell/haswell_init.c
+++ b/src/cpu/intel/haswell/haswell_init.c
@@ -446,12 +446,6 @@ static void configure_c_states(void)
/* The deepest package c-state defaults to factory-configured value. */
wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr);
- msr = rdmsr(MSR_PMG_IO_CAPTURE_BASE);
- msr.lo &= ~0xffff;
- msr.lo |= (get_pmbase() + 0x14); // LVL_2 base address
- /* The deepest package c-state defaults to factory-configured value. */
- wrmsr(MSR_PMG_IO_CAPTURE_BASE, msr);
-
msr = rdmsr(MSR_MISC_PWR_MGMT);
msr.lo &= ~(1 << 0); // Enable P-state HW_ALL coordination
wrmsr(MSR_MISC_PWR_MGMT, msr);