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authorDuncan Laurie <dlaurie@chromium.org>2012-01-06 15:49:30 -0800
committerStefan Reinauer <stefan.reinauer@coreboot.org>2012-03-30 17:55:55 +0200
commit527fc74a83a7b0fdeebfeb9ddd5890f11f01c102 (patch)
treefeba89dc9fbff816641496e77ba38da0b6f3f4dc /src/cpu
parent7389fa945f48c6da6e5f39d871c0efd9dfba93a1 (diff)
downloadcoreboot-527fc74a83a7b0fdeebfeb9ddd5890f11f01c102.tar.xz
Fix MB calculation in the reporting of the MTRR hole
Change-Id: I34b5c4ffd2a3f3e895d2bffedce1c00ee9aea942 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: http://review.coreboot.org/763 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/x86/mtrr/mtrr.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c
index 8dccfefa04..5f5e02bbb1 100644
--- a/src/cpu/x86/mtrr/mtrr.c
+++ b/src/cpu/x86/mtrr/mtrr.c
@@ -306,7 +306,7 @@ static unsigned int range_to_mtrr(unsigned int reg,
if (hole_sizek) {
printk(BIOS_DEBUG, "Adding hole at %ldMB-%ldMB\n",
- hole_startk, hole_startk + hole_sizek);
+ hole_startk >> 10, (hole_startk + hole_sizek) >> 10);
reg = range_to_mtrr(reg, hole_startk, hole_sizek,
next_range_startk, MTRR_TYPE_UNCACHEABLE,
address_bits, above4gb);