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authorMyles Watson <mylesgw@gmail.com>2009-07-01 16:34:03 +0000
committerMyles Watson <mylesgw@gmail.com>2009-07-01 16:34:03 +0000
commit6c96517a132ce26f906c8e38e19ebaab8b736e9a (patch)
treef0c455b4c318188f673bbd4a15bdc76a17c21761 /src/cpu
parent08405e74119bde819bb892b55e14e407d7ad5617 (diff)
downloadcoreboot-6c96517a132ce26f906c8e38e19ebaab8b736e9a.tar.xz
Fix typo and only output post code if the work was done.
Thanks to Thomas Jourdan <thomas.jourdan@gmail.com> for reporting it. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4391 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/intel/model_6fx/cache_as_ram_post.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/cpu/intel/model_6fx/cache_as_ram_post.c b/src/cpu/intel/model_6fx/cache_as_ram_post.c
index 8e50cd2641..e3246348c1 100644
--- a/src/cpu/intel/model_6fx/cache_as_ram_post.c
+++ b/src/cpu/intel/model_6fx/cache_as_ram_post.c
@@ -50,9 +50,9 @@
"wrmsr\n"
"movl $MTRRphysMask_MSR(1), %ecx\n"
"wrmsr\n"
-#endif
"movb $0x33, %al\noutb %al, $0x80\n"
+#endif
#ifdef CLEAR_FIRST_1M_RAM
"movb $0x34, %al\noutb %al, $0x80\n"
/* Enable Write Combining and Speculative Reads for the first 1MB */
@@ -120,7 +120,7 @@
"movb $0x3b, %al\noutb %al, $0x80\n"
/* Enable prefetchers */
- "movl $0x01a0, %eax\n"
+ "movl $0x01a0, %ecx\n"
"rdmsr\n"
"andl $~((1 << 9) | (1 << 19)), %eax\n"
"andl $~((1 << 5) | (1 << 7)), %edx\n"