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authorKyösti Mälkki <kyosti.malkki@gmail.com>2017-09-02 16:20:15 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2017-09-06 04:59:09 +0000
commit7076aa5745babc188275a837797d5f0f0b7db5d8 (patch)
tree55d4d703987aabbdf42678f5fff222f15969ab7c /src/cpu
parent5fb2d3074fce9404440dfb81610f66c9c95d78d3 (diff)
downloadcoreboot-7076aa5745babc188275a837797d5f0f0b7db5d8.tar.xz
AGESA: Rename assembly from .inc to .S
Change-Id: I5f90df92e0ac27e98edf23784eeec5618d150430 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21378 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/amd/agesa/Makefile.inc2
-rw-r--r--src/cpu/amd/agesa/cache_as_ram.S (renamed from src/cpu/amd/agesa/cache_as_ram.inc)11
-rw-r--r--src/cpu/amd/pi/Makefile.inc2
3 files changed, 8 insertions, 7 deletions
diff --git a/src/cpu/amd/agesa/Makefile.inc b/src/cpu/amd/agesa/Makefile.inc
index 1d5e705277..d9c5f704e0 100644
--- a/src/cpu/amd/agesa/Makefile.inc
+++ b/src/cpu/amd/agesa/Makefile.inc
@@ -24,7 +24,7 @@ ramstage-y += s3_mtrr.c
ifeq ($(CONFIG_AGESA_LEGACY), y)
cpu_incs-y += $(src)/cpu/amd/agesa/cache_as_ram_legacy.inc
else
-cpu_incs-y += $(src)/cpu/amd/agesa/cache_as_ram.inc
+cpu_incs-y += $(src)/cpu/amd/agesa/cache_as_ram.S
romstage-y += romstage.c
endif
diff --git a/src/cpu/amd/agesa/cache_as_ram.inc b/src/cpu/amd/agesa/cache_as_ram.S
index cfad2f7d1a..b96a5e70e4 100644
--- a/src/cpu/amd/agesa/cache_as_ram.inc
+++ b/src/cpu/amd/agesa/cache_as_ram.S
@@ -16,20 +16,21 @@
/******************************************************************************
* AMD Generic Encapsulated Software Architecture
*
- * $Workfile:: cache_as_ram.inc
+ * $Workfile:: cache_as_ram.S
*
- * Description: cache_as_ram.inc - AGESA Module Entry Point for GCC complier
+ * Description: cache_as_ram.S - AGESA Module Entry Point for GCC complier
*
******************************************************************************
*/
#include "gcccar.inc"
#include <cpu/x86/cache.h>
+#include <cpu/x86/post_code.h>
.code32
-.globl cache_as_ram_setup, cache_as_ram_setup_out
+.globl _cache_as_ram_setup, _cache_as_ram_setup_end
-cache_as_ram_setup:
+_cache_as_ram_setup:
/* Preserve BIST. */
movd %eax, %mm0
@@ -130,4 +131,4 @@ disable_cache_as_ram:
stop:
jmp stop
-cache_as_ram_setup_out:
+_cache_as_ram_setup_end:
diff --git a/src/cpu/amd/pi/Makefile.inc b/src/cpu/amd/pi/Makefile.inc
index 3171bb5d67..af24b48001 100644
--- a/src/cpu/amd/pi/Makefile.inc
+++ b/src/cpu/amd/pi/Makefile.inc
@@ -17,7 +17,7 @@ subdirs-$(CONFIG_CPU_AMD_PI_00630F01) += 00630F01
subdirs-$(CONFIG_CPU_AMD_PI_00730F01) += 00730F01
subdirs-$(CONFIG_CPU_AMD_PI_00660F01) += 00660F01
-cpu_incs-y += $(src)/cpu/amd/agesa/cache_as_ram.inc
+cpu_incs-y += $(src)/cpu/amd/agesa/cache_as_ram.S
ifeq ($(CONFIG_BINARYPI_LEGACY_WRAPPER), y)
romstage-y += romstage.c