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authorRonald G. Minnich <rminnich@gmail.com>2013-04-09 14:39:34 -0700
committerRonald G. Minnich <rminnich@gmail.com>2013-04-10 17:37:25 +0200
commit7576f2515ed81a67e6271cb6a88fa94b626e2938 (patch)
tree34bee15a954e391ee7b01bfe803faf7f069af226 /src/cpu
parent765ff76d8f1c09fefdc533b2facd0d99b1787eca (diff)
downloadcoreboot-7576f2515ed81a67e6271cb6a88fa94b626e2938.tar.xz
GOOGLE/SNOW: add edp support to ramstage
Add basic edp support to the ramstage. Not working. Change-Id: I15086e03417edca7426c214e67b51719d8ed9341 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/3055 Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/samsung/exynos5-common/exynos-fb.c38
-rw-r--r--src/cpu/samsung/exynos5-common/s5p-dp-core.h1
-rw-r--r--src/cpu/samsung/exynos5-common/s5p-dp-reg.c18
3 files changed, 32 insertions, 25 deletions
diff --git a/src/cpu/samsung/exynos5-common/exynos-fb.c b/src/cpu/samsung/exynos5-common/exynos-fb.c
index 615a720ead..b57e27631f 100644
--- a/src/cpu/samsung/exynos5-common/exynos-fb.c
+++ b/src/cpu/samsung/exynos5-common/exynos-fb.c
@@ -203,7 +203,7 @@ static int s5p_dp_config_video(struct s5p_dp_device *dp,
video_info->ycbcr_coeff);
if (s5p_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
- debug("PLL is not locked yet.\n");
+ printk(BIOS_DEBUG, "PLL is not locked yet.\n");
return -ERR_PLL_NOT_UNLOCKED;
}
@@ -216,7 +216,7 @@ static int s5p_dp_config_video(struct s5p_dp_device *dp,
} while (get_timer(start) <= STREAM_ON_TIMEOUT);
if (!timeout) {
- debug("Video Clock Not ok\n");
+ printk(BIOS_DEBUG, "Video Clock Not ok\n");
return -ERR_VIDEO_CLOCK_BAD;
}
@@ -236,7 +236,7 @@ static int s5p_dp_config_video(struct s5p_dp_device *dp,
timeout = s5p_dp_is_video_stream_on(dp);
if (timeout) {
- debug("Video Stream Not on\n");
+ printk(BIOS_DEBUG, "Video Stream Not on\n");
return -ERR_VIDEO_STREAM_BAD;
}
@@ -253,14 +253,14 @@ static int s5p_dp_enable_rx_to_enhanced_mode(struct s5p_dp_device *dp)
u8 data;
if (s5p_dp_read_byte_from_dpcd(dp, DPCD_ADDR_LANE_COUNT_SET, &data)) {
- debug("DPCD read error\n");
+ printk(BIOS_DEBUG, "DPCD read error\n");
return -ERR_DPCD_READ_ERROR1;
}
if (s5p_dp_write_byte_to_dpcd(dp, DPCD_ADDR_LANE_COUNT_SET,
DPCD_ENHANCED_FRAME_EN |
(data & DPCD_LANE_COUNT_SET_MASK))) {
- debug("DPCD write error\n");
+ printk(BIOS_DEBUG, "DPCD write error\n");
return -ERR_DPCD_WRITE_ERROR1;
}
@@ -281,13 +281,13 @@ static int s5p_dp_enable_scramble(struct s5p_dp_device *dp)
if (s5p_dp_read_byte_from_dpcd(dp, DPCD_ADDR_TRAINING_PATTERN_SET,
&data)) {
- debug("DPCD read error\n");
+ printk(BIOS_DEBUG, "DPCD read error\n");
return -ERR_DPCD_READ_ERROR2;
}
if (s5p_dp_write_byte_to_dpcd(dp, DPCD_ADDR_TRAINING_PATTERN_SET,
(u8)(data & ~DPCD_SCRAMBLING_DISABLED))) {
- debug("DPCD write error\n");
+ printk(BIOS_DEBUG, "DPCD write error\n");
return -ERR_DPCD_WRITE_ERROR2;
}
@@ -314,10 +314,10 @@ static int s5p_dp_init_dp(struct s5p_dp_device *dp)
break;
udelay(5000);
- debug("LCD retry init, attempt=%d ret=%d\n", i, ret);
+ printk(BIOS_DEBUG, "LCD retry init, attempt=%d ret=%d\n", i, ret);
}
if (i == DP_INIT_TRIES) {
- debug("LCD initialization failed, ret=%d\n", ret);
+ printk(BIOS_DEBUG, "LCD initialization failed, ret=%d\n", ret);
return ret;
}
@@ -356,7 +356,7 @@ static int s5p_dp_set_lane_lane_pre_emphasis(struct s5p_dp_device *dp,
writel(reg, &base->ln3_link_trn_ctl);
break;
default:
- debug("%s: Invalid lane %d\n", __func__, lane);
+ printk(BIOS_DEBUG, "%s: Invalid lane %d\n", __func__, lane);
return -ERR_INVALID_LANE;
}
return 0;
@@ -438,7 +438,7 @@ static int s5p_dp_hw_link_training(struct s5p_dp_device *dp,
for (lane = 0; lane < max_lane; lane++)
if (s5p_dp_set_lane_lane_pre_emphasis(dp,
PRE_EMPHASIS_LEVEL_0, lane)) {
- debug("Unable to set pre emphasis level\n");
+ printk(BIOS_DEBUG, "Unable to set pre emphasis level\n");
return -ERR_PRE_EMPHASIS_LEVELS;
}
@@ -451,14 +451,14 @@ static int s5p_dp_hw_link_training(struct s5p_dp_device *dp,
if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
(dp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
- debug("Rx Max Link Rate is abnormal :%x !\n",
+ printk(BIOS_DEBUG, "Rx Max Link Rate is abnormal :%x !\n",
dp->link_train.link_rate);
/* Not Retrying */
return -ERR_LINK_RATE_ABNORMAL;
}
if (dp->link_train.lane_count == 0) {
- debug("Rx Max Lane count is abnormal :%x !\n",
+ printk(BIOS_DEBUG, "Rx Max Lane count is abnormal :%x !\n",
dp->link_train.lane_count);
/* Not retrying */
return -ERR_MAX_LANE_COUNT_ABNORMAL;
@@ -487,7 +487,7 @@ static int s5p_dp_hw_link_training(struct s5p_dp_device *dp,
/* Get hardware link training status */
data = readl(&base->dp_hw_link_training);
if (data != 0) {
- debug(" H/W link training failure: 0x%x\n", data);
+ printk(BIOS_DEBUG, " H/W link training failure: 0x%x\n", data);
return -ERR_LINK_TRAINING_FAILURE;
}
@@ -521,14 +521,14 @@ int dp_controller_init(struct s5p_dp_device *dp_device, unsigned *wait_ms)
power_enable_dp_phy();
ret = s5p_dp_init_dp(dp);
if (ret) {
- debug("%s: Could not initialize dp\n", __func__);
+ printk(BIOS_DEBUG, "%s: Could not initialize dp\n", __func__);
return ret;
}
ret = s5p_dp_hw_link_training(dp, dp->video_info->lane_count,
dp->video_info->link_rate);
if (ret) {
- debug("unable to do link train\n");
+ printk(BIOS_DEBUG, "unable to do link train\n");
return ret;
}
/* Minimum delay after H/w Link training */
@@ -536,13 +536,13 @@ int dp_controller_init(struct s5p_dp_device *dp_device, unsigned *wait_ms)
ret = s5p_dp_enable_scramble(dp);
if (ret) {
- debug("unable to set scramble mode\n");
+ printk(BIOS_DEBUG, "unable to set scramble mode\n");
return ret;
}
ret = s5p_dp_enable_rx_to_enhanced_mode(dp);
if (ret) {
- debug("unable to set enhanced mode\n");
+ printk(BIOS_DEBUG, "unable to set enhanced mode\n");
return ret;
}
@@ -557,7 +557,7 @@ int dp_controller_init(struct s5p_dp_device *dp_device, unsigned *wait_ms)
s5p_dp_init_video(dp);
ret = s5p_dp_config_video(dp, dp->video_info);
if (ret) {
- debug("unable to config video\n");
+ printk(BIOS_DEBUG, "unable to config video\n");
return ret;
}
diff --git a/src/cpu/samsung/exynos5-common/s5p-dp-core.h b/src/cpu/samsung/exynos5-common/s5p-dp-core.h
index 67c1990cfd..2988d5d248 100644
--- a/src/cpu/samsung/exynos5-common/s5p-dp-core.h
+++ b/src/cpu/samsung/exynos5-common/s5p-dp-core.h
@@ -250,6 +250,7 @@ void s5p_dp_config_video_slave_mode(struct s5p_dp_device *dp,
void s5p_dp_wait_hw_link_training_done(struct s5p_dp_device *dp);
/* startup and init */
+struct exynos5_fimd_panel;
void fb_init(vidinfo_t *panel_info, void *lcdbase, struct exynos5_fimd_panel *pd);
int dp_controller_init(struct s5p_dp_device *dp_device, unsigned *wait_ms);
int lcd_ctrl_init(vidinfo_t *panel_info, struct exynos5_fimd_panel *panel_data, void *lcdbase);
diff --git a/src/cpu/samsung/exynos5-common/s5p-dp-reg.c b/src/cpu/samsung/exynos5-common/s5p-dp-reg.c
index adb64a8e10..60e1398ba4 100644
--- a/src/cpu/samsung/exynos5-common/s5p-dp-reg.c
+++ b/src/cpu/samsung/exynos5-common/s5p-dp-reg.c
@@ -19,6 +19,8 @@
#include "cpu/samsung/exynos5250/fimd.h"
#include "s5p-dp-core.h"
+#include <console/console.h>
+
void s5p_dp_reset(struct s5p_dp_device *dp)
{
u32 reg;
@@ -127,7 +129,7 @@ int s5p_dp_init_analog_func(struct s5p_dp_device *dp)
start = get_timer(0);
while (s5p_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
if (get_timer(start) > PLL_LOCK_TIMEOUT) {
- debug("%s: PLL is not locked yet\n", __func__);
+ printk(BIOS_DEBUG, "%s: PLL is not locked yet\n", __func__);
return -1;
}
}
@@ -174,6 +176,9 @@ int s5p_dp_start_aux_transaction(struct s5p_dp_device *dp)
/* Enable AUX CH operation */
setbits_le32(&base->aux_ch_ctl_2, AUX_EN);
+ printk(BIOS_DEBUG, "%s: base: 0x%p, &base->aux_ch_ctl_2: 0x%p, aux_ch_ctl_2: 0x%08x\n",
+ __func__, base, &base->aux_ch_ctl_2, readl(&base->aux_ch_ctl_2));
+
/* Is AUX CH command reply received? */
reg = readl(&base->dp_int_sta);
while (!(reg & RPLY_RECEIV))
@@ -184,6 +189,7 @@ int s5p_dp_start_aux_transaction(struct s5p_dp_device *dp)
/* Clear interrupt source for AUX CH access error */
reg = readl(&base->dp_int_sta);
+ printk(BIOS_DEBUG, "%s: dp_int_sta: 0x%02x\n", __func__, reg);
if (reg & AUX_ERR) {
writel(AUX_ERR, &base->dp_int_sta);
return -1;
@@ -192,7 +198,7 @@ int s5p_dp_start_aux_transaction(struct s5p_dp_device *dp)
/* Check AUX CH error access status */
reg = readl(&base->dp_int_sta);
if ((reg & AUX_STATUS_MASK) != 0) {
- debug("AUX CH error happens: %d\n\n",
+ printk(BIOS_DEBUG, "AUX CH error happens: %d\n\n",
reg & AUX_STATUS_MASK);
return -1;
}
@@ -241,7 +247,7 @@ int s5p_dp_write_byte_to_dpcd(struct s5p_dp_device *dp,
if (retval == 0)
break;
else
- debug("Aux Transaction fail!\n");
+ printk(BIOS_DEBUG, "Aux Transaction fail!\n");
}
return retval;
@@ -284,7 +290,7 @@ int s5p_dp_read_byte_from_dpcd(struct s5p_dp_device *dp,
if (retval == 0)
break;
else
- debug("Aux Transaction fail!\n");
+ printk(BIOS_DEBUG, "Aux Transaction fail!\n");
}
/* Read data buffer */
@@ -359,7 +365,7 @@ int s5p_dp_is_slave_video_stream_clock_on(struct s5p_dp_device *dp)
reg = readl(&base->sys_ctl_2);
if (reg & CHA_STA) {
- debug("Input stream clk is changing\n");
+ printk(BIOS_DEBUG, "Input stream clk is changing\n");
return -1;
}
@@ -433,7 +439,7 @@ int s5p_dp_is_video_stream_on(struct s5p_dp_device *dp)
} while (get_timer(start) <= STREAM_ON_TIMEOUT);
if (i != 4) {
- debug("s5p_dp_is_video_stream_on timeout\n");
+ printk(BIOS_DEBUG, "s5p_dp_is_video_stream_on timeout\n");
return -1;
}