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| author | Aaron Durbin <adurbin@chromium.org> | 2016-10-28 17:32:24 -0500 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-10-31 19:34:20 +0100 |
| commit | 8cd723bc0cb64f28b1009fd2fa55f6680a402b61 (patch) | |
| tree | 97aad8d8164e39d12b0c710f6a16b59950a367c7 /src/cpu | |
| parent | 9a2790e328c4cabefa201995aa4812be414d93c3 (diff) | |
| download | coreboot-8cd723bc0cb64f28b1009fd2fa55f6680a402b61.tar.xz | |
lib/prog_loaders: use common ramstage_cache_invalid()
All current implementations of ramstage_cache_invalid() were just
resetting the system based on the RESET_ON_INVALID_RAMSTAGE_CACHE
Kconfig option. Move that behavior to a single implementation
within prog_loaders.c which removes duplication.
Change-Id: I67aae73f9e1305732f90d947fe57c5aaf66ada9e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17184
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/intel/haswell/romstage.c | 10 |
1 files changed, 0 insertions, 10 deletions
diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 8b62d43e2b..f823c55b0c 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -264,13 +264,3 @@ void asmlinkage romstage_after_car(void) /* Load the ramstage. */ run_ramstage(); } - - -#if IS_ENABLED(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) -void ramstage_cache_invalid(void) -{ -#if CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE - reset_system(); -#endif -} -#endif |