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| author | Michael Niewöhner <foss@mniewoehner.de> | 2020-10-13 22:58:28 +0200 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2020-10-16 22:20:47 +0000 |
| commit | 90df9166834f26a7600d089bc2fade0f34fd6681 (patch) | |
| tree | 19123d60f02b305111e513c262952f0f9a379705 /src/cpu | |
| parent | d32bb116f063d04e0c5f72e6fd0367d6e542c9fb (diff) | |
| download | coreboot-90df9166834f26a7600d089bc2fade0f34fd6681.tar.xz | |
include/cpu/x86: introduce new helper for (un)setting MSRs
msr_set_bit can only set single bits in MSRs and causes mixing of bit
positions and bitmasks in the MSR header files. Thus, replace the helper
by versions which can unset and set whole MSR bitmasks, just like the
"and-or"-helper, but in the way commit 64a6b6c was done (inversion done
in the helper). This helps keeping the MSR macros unified in bitmask
style.
In sum, the three helpers msr_set, msr_unset and msr_unset_and_set get
added.
The few uses of msr_set_bit have been replaced by the new version, while
the used macros have been converted accordingly.
Change-Id: Idfe9b66e7cfe78ec295a44a2a193f530349f7689
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46354
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/intel/haswell/finalize.c | 3 | ||||
| -rw-r--r-- | src/cpu/intel/model_2065x/finalize.c | 7 | ||||
| -rw-r--r-- | src/cpu/intel/model_206ax/finalize.c | 7 |
3 files changed, 10 insertions, 7 deletions
diff --git a/src/cpu/intel/haswell/finalize.c b/src/cpu/intel/haswell/finalize.c index 1832e63967..3bf9225a1f 100644 --- a/src/cpu/intel/haswell/finalize.c +++ b/src/cpu/intel/haswell/finalize.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <types.h> #include <arch/cpu.h> #include <cpu/x86/msr.h> #include "haswell.h" @@ -7,5 +8,5 @@ void intel_cpu_haswell_finalize_smm(void) { /* Lock memory configuration to protect SMM */ - msr_set_bit(MSR_LT_LOCK_MEMORY, 0); + msr_set(MSR_LT_LOCK_MEMORY, BIT(0)); } diff --git a/src/cpu/intel/model_2065x/finalize.c b/src/cpu/intel/model_2065x/finalize.c index d530fba5e7..d19ddf7a34 100644 --- a/src/cpu/intel/model_2065x/finalize.c +++ b/src/cpu/intel/model_2065x/finalize.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <types.h> #include <arch/cpu.h> #include <cpu/x86/msr.h> #include <cpu/intel/speedstep.h> @@ -13,12 +14,12 @@ void intel_model_2065x_finalize_smm(void) { /* Lock C-State MSR */ - msr_set_bit(MSR_PKG_CST_CONFIG_CONTROL, 15); + msr_set(MSR_PKG_CST_CONFIG_CONTROL, BIT(15)); /* Lock AES-NI only if supported */ if (cpuid_ecx(1) & (1 << 25)) - msr_set_bit(MSR_FEATURE_CONFIG, 0); + msr_set(MSR_FEATURE_CONFIG, BIT(0)); /* Lock TM interrupts - route thermal events to all processors */ - msr_set_bit(MSR_MISC_PWR_MGMT, 22); + msr_set(MSR_MISC_PWR_MGMT, BIT(22)); } diff --git a/src/cpu/intel/model_206ax/finalize.c b/src/cpu/intel/model_206ax/finalize.c index 37fbefdf13..98be012746 100644 --- a/src/cpu/intel/model_206ax/finalize.c +++ b/src/cpu/intel/model_206ax/finalize.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <types.h> #include <arch/cpu.h> #include <cpu/x86/msr.h> #include "model_206ax.h" @@ -13,11 +14,11 @@ void intel_model_206ax_finalize_smm(void) { /* Lock AES-NI only if supported */ if (cpuid_ecx(1) & (1 << 25)) - msr_set_bit(MSR_FEATURE_CONFIG, 0); + msr_set(MSR_FEATURE_CONFIG, BIT(0)); /* Lock TM interrupts - route thermal events to all processors */ - msr_set_bit(MSR_MISC_PWR_MGMT, 22); + msr_set(MSR_MISC_PWR_MGMT, BIT(22)); /* Lock memory configuration to protect SMM */ - msr_set_bit(MSR_LT_LOCK_MEMORY, 0); + msr_set(MSR_LT_LOCK_MEMORY, BIT(0)); } |