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authorTimothy Pearson <tpearson@raptorengineeringinc.com>2016-01-05 11:00:49 -0600
committerMartin Roth <martinroth@google.com>2016-01-06 17:46:21 +0100
commitbfa19e1e47e7f383a45c9e6955c7968c3b926540 (patch)
tree565c6f1da08b9ad516fac7b4b8484a8af43bb58f /src/cpu
parentbb826ef661f7ff390e284bcae6b0b330ca48ceb3 (diff)
downloadcoreboot-bfa19e1e47e7f383a45c9e6955c7968c3b926540.tar.xz
cpu/amd/fam10h-15h: Add tsc_freq_mhz() function
The AMD Family 10h/15h processors use a TSC that increments at the P0 core frequency. Allow coreboot to query the TSC frequency. Change-Id: I73ead4fd4af18991452d59985b667a54689778cd Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12834 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/amd/family_10h-family_15h/Makefile.inc2
-rw-r--r--src/cpu/amd/family_10h-family_15h/tsc_freq.c37
2 files changed, 39 insertions, 0 deletions
diff --git a/src/cpu/amd/family_10h-family_15h/Makefile.inc b/src/cpu/amd/family_10h-family_15h/Makefile.inc
index 6cd2513a6d..f10f7327e4 100644
--- a/src/cpu/amd/family_10h-family_15h/Makefile.inc
+++ b/src/cpu/amd/family_10h-family_15h/Makefile.inc
@@ -3,6 +3,8 @@ ramstage-y += model_10xxx_init.c
ramstage-y += processor_name.c
romstage-y += update_microcode.c
+romstage-y += tsc_freq.c
+ramstage-y += tsc_freq.c
romstage-y += ram_calc.c
ramstage-y += ram_calc.c
ramstage-y += monotonic_timer.c
diff --git a/src/cpu/amd/family_10h-family_15h/tsc_freq.c b/src/cpu/amd/family_10h-family_15h/tsc_freq.c
new file mode 100644
index 0000000000..afd7dab69f
--- /dev/null
+++ b/src/cpu/amd/family_10h-family_15h/tsc_freq.c
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Raptor Engineering
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/tsc.h>
+
+unsigned long tsc_freq_mhz(void)
+{
+ msr_t msr;
+ uint8_t cpufid;
+ uint8_t cpudid;
+
+ /* On Family 10h/15h CPUs the TSC increments
+ * at the P0 clock rate. Read the P0 clock
+ * frequency from the P0 MSR and convert
+ * to MHz. See also the Family 15h BKDG
+ * Rev. 3.14 page 569.
+ */
+ msr = rdmsr(0xc0010064);
+ cpufid = (msr.lo & 0x3f);
+ cpudid = (msr.lo & 0x1c0) >> 6;
+
+ return (100 * (cpufid + 0x10)) / (0x01 << cpudid);
+}