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| author | Stefan Reinauer <reinauer@chromium.org> | 2012-07-10 17:02:21 -0700 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2012-07-26 00:19:57 +0200 |
| commit | c65a36eb0f097ca13cdab8a787ce5cf35f49a64f (patch) | |
| tree | 60ccd686753137e1422b2b3a2546104fee8e765f /src/cpu | |
| parent | 79bbbd9db36d93a8a8a1b9d27ef32a69991e6b30 (diff) | |
| download | coreboot-c65a36eb0f097ca13cdab8a787ce5cf35f49a64f.tar.xz | |
Enable Microcode in CBFS for all SandyBridge/IvyBridge systems
Change-Id: Idee4facc18e0be60906d2a2f0e99bd39de8d7247
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1332
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/Kconfig | 5 | ||||
| -rw-r--r-- | src/cpu/intel/model_206ax/Kconfig | 4 | ||||
| -rw-r--r-- | src/cpu/intel/model_206ax/bootblock.c | 10 | ||||
| -rw-r--r-- | src/cpu/intel/model_206ax/model_206ax_init.c | 10 |
4 files changed, 2 insertions, 27 deletions
diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index f37bbf6755..baf686ea75 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -62,13 +62,10 @@ config SSE2 streaming SIMD instructions. Some parts of coreboot can be built with more efficient code if SSE2 instructions are available. -if CPU_INTEL_MODEL_206AX || CPU_INTEL_MODEL_306AX - config MICROCODE_IN_CBFS bool "Look for microcode in CBFS" + default n help Load microcode updates from CBFS instead of compiling them in. -endif - endif # ARCH_X86 diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index 1d4ff02b36..071683ea0f 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -12,6 +12,7 @@ config CPU_SPECIFIC_OPTIONS select SSE2 select UDELAY_LAPIC select SMM_TSEG + select MICROCODE_IN_CBFS config BOOTBLOCK_CPU_INIT string @@ -21,14 +22,11 @@ config SMM_TSEG_SIZE hex default 0x800000 -if MICROCODE_IN_CBFS config MICROCODE_INCLUDE_PATH string default "src/cpu/intel/model_206ax" endif -endif - if CPU_INTEL_MODEL_206AX config CPU_MODEL_NAME string diff --git a/src/cpu/intel/model_206ax/bootblock.c b/src/cpu/intel/model_206ax/bootblock.c index dbc35914cb..02958bbc85 100644 --- a/src/cpu/intel/model_206ax/bootblock.c +++ b/src/cpu/intel/model_206ax/bootblock.c @@ -25,12 +25,6 @@ #include <arch/io.h> #include <arch/romcc_io.h> -#if !CONFIG_MICROCODE_IN_CBFS -static const uint32_t microcode_updates[] = { - #include "microcode_blob.h" -}; -#endif - #include <cpu/intel/microcode/microcode.c> #include "model_206ax.h" @@ -125,9 +119,5 @@ static void bootblock_cpu_init(void) /* Set flex ratio and reset if needed */ set_flex_ratio_to_tdp_nominal(); enable_rom_caching(); -#if CONFIG_MICROCODE_IN_CBFS intel_update_microcode_from_cbfs(); -#else - intel_update_microcode(microcode_updates); -#endif } diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index 08757d138a..70a655a6f0 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -115,12 +115,6 @@ static acpi_cstate_t cstate_map[] = { { 0 } }; -#if !CONFIG_MICROCODE_IN_CBFS -static const uint32_t microcode_updates[] = { - #include "microcode_blob.h" -}; -#endif - /* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */ static const u8 power_limit_time_sec_to_msr[] = { [0] = 0x00, @@ -421,11 +415,7 @@ static void model_206ax_init(device_t cpu) /* Turn on caching if we haven't already */ x86_enable_cache(); -#if CONFIG_MICROCODE_IN_CBFS intel_update_microcode_from_cbfs(); -#else - intel_update_microcode(microcode_updates); -#endif /* Clear out pending MCEs */ configure_mca(); |