diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2018-08-06 15:00:25 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-10-24 10:04:17 +0000 |
| commit | cf2941aec237535ff76961646ad67b71f0a03a60 (patch) | |
| tree | a91f3823c402eebdc7dfe178cbcc3b0be65bc037 /src/cpu | |
| parent | e19d61b4e82779c4161a8433d58b2d5706f2d3e1 (diff) | |
| download | coreboot-cf2941aec237535ff76961646ad67b71f0a03a60.tar.xz | |
cpu/intel/smm: Don't make assumptions on TSEG_SIZE
Do not assume:
- TSEG is 8M
- IED_REGION_SIZE is set (not needed on older platforms).
Change-Id: I1aadc6f0459a8035864dcf02b0a07e00b284fe2a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27872
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/intel/smm/gen1/smmrelocate.c | 31 |
1 files changed, 21 insertions, 10 deletions
diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c index 7c492179fe..15caa0f57b 100644 --- a/src/cpu/intel/smm/gen1/smmrelocate.c +++ b/src/cpu/intel/smm/gen1/smmrelocate.c @@ -16,6 +16,7 @@ /* SMM relocation with intention to work for i945-ivybridge. Right now used for sandybridge and ivybridge. */ +#include <assert.h> #include <types.h> #include <string.h> #include <device/device.h> @@ -120,10 +121,15 @@ static void asmlinkage cpu_smm_do_relocation(void *arg) * size * CPU num. */ save_state->smbase = relo_params->smram_base - cpu * runtime->save_state_size; - save_state->iedbase = relo_params->ied_base; + if (CONFIG_IED_REGION_SIZE != 0) { + save_state->iedbase = relo_params->ied_base; - printk(BIOS_DEBUG, "New SMBASE=0x%08x IEDBASE=0x%08x @ %p\n", - save_state->smbase, save_state->iedbase, save_state); + printk(BIOS_DEBUG, "New SMBASE=0x%08x IEDBASE=0x%08x @ %p\n", + save_state->smbase, save_state->iedbase, save_state); + } else { + printk(BIOS_DEBUG, "New SMBASE=0x%08x @ %p\n", + save_state->smbase, save_state); + } /* Write SMRR MSRs based on indicated support. */ mtrr_cap = rdmsr(MTRR_CAP_MSR); @@ -144,16 +150,20 @@ static void fill_in_relocation_params(struct smm_relocation_params *params) configuration value instead. */ const u32 tseg_size = northbridge_get_tseg_size(); - /* The SMRAM available to the handler is 4MiB - since the IEDRAM lives at TSEGMB + 4MiB. */ params->smram_base = tsegmb; - params->smram_size = 4 << 20; - params->ied_base = tsegmb + params->smram_size; - params->ied_size = tseg_size - params->smram_size; + params->smram_size = tseg_size; + if (CONFIG_IED_REGION_SIZE != 0) { + ASSERT(params->smram_size > CONFIG_IED_REGION_SIZE); + params->smram_size -= CONFIG_IED_REGION_SIZE; + params->ied_base = tsegmb + tseg_size - CONFIG_IED_REGION_SIZE; + params->ied_size = CONFIG_IED_REGION_SIZE; + } /* Adjust available SMM handler memory size. */ - if (IS_ENABLED(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM)) + if (IS_ENABLED(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM)) { + ASSERT(params->smram_size > CONFIG_SMM_RESERVED_SIZE); params->smram_size -= CONFIG_SMM_RESERVED_SIZE; + } if (IS_ALIGNED(tsegmb, tseg_size)) { /* SMRR has 32-bits of valid address aligned to 4KiB. */ @@ -259,7 +269,8 @@ static int cpu_smm_setup(void) /* enable the SMM memory window */ northbridge_write_smram(D_OPEN | G_SMRAME | C_BASE_SEG); - setup_ied_area(&smm_reloc_params); + if (CONFIG_IED_REGION_SIZE != 0) + setup_ied_area(&smm_reloc_params); num_cpus = cpu_get_apic_id_map(apic_id_map); if (num_cpus > CONFIG_MAX_CPUS) { |